path: root/src/mainboard/nvidia/l1_2pvv/Options.lb

##
## This file is part of the coreboot project.
##
## Copyright (C) 2007 AMD
## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses HAVE_ACPI_TABLES
uses ACPI_SSDTX_NUM
uses USE_FALLBACK_IMAGE
uses USE_FAILOVER_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_FAILOVER_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses FAILOVER_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_USBDEBUG_DIRECT
uses CONFIG_PCI_ROM_RUN
uses HW_MEM_HOLE_SIZEK
uses HW_MEM_HOLE_SIZE_AUTO_INC
uses K8_HT_FREQ_1G_SUPPORT

uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
uses SB_HT_CHAIN_UNITID_OFFSET_ONLY

uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_INIT

uses SERIAL_CPU_INIT

uses ENABLE_APIC_EXT_ID
uses APIC_ID_OFFSET
uses LIFT_BSP_APIC_ID

uses CONFIG_PCI_64BIT_PREF_MEM

uses CONFIG_LB_MEM_TOPK

uses CONFIG_AP_CODE_IN_CAR

uses MEM_TRAIN_SEQ

uses WAIT_BEFORE_CPUS_INIT

uses CONFIG_USE_PRINTK_IN_CAR

###
### Build options
###

##
## ROM_SIZE is the size of boot ROM that this board will use.
##
default ROM_SIZE=524288
#default ROM_SIZE=0x100000

##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
#default FALLBACK_SIZE=131072
#default FALLBACK_SIZE=0x40000

#FALLBACK: 256K-4K
default FALLBACK_SIZE=0x3f000
#FAILOVER: 4K
default FAILOVER_SIZE=0x01000

#more 1M for pgtbl
default CONFIG_LB_MEM_TOPK=2048

##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
default HAVE_FAILOVER_BOOT=1

##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1

##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=11

##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1

## ACPI tables will be included
default HAVE_ACPI_TABLES=0

##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1

##
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123

##
## Build code for SMP support
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1

#default SERIAL_CPU_INIT=0

default ENABLE_APIC_EXT_ID=0
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=1

#CHIP_NAME ?
default CONFIG_CHIP_NAME=1

#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
#default HW_MEM_HOLE_SIZEK=0x200000
#1G
default HW_MEM_HOLE_SIZEK=0x100000
#512M
#default HW_MEM_HOLE_SIZEK=0x80000

#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
#default HW_MEM_HOLE_SIZE_AUTO_INC=1

#Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1

#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1

#default CONFIG_USBDEBUG_DIRECT=1

#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
default HT_CHAIN_UNITID_BASE=0

#real SB Unit ID, default is 0x20, mean dont touch it at last
#default HT_CHAIN_END_UNITID_BASE=0x6

#make the SB HT chain on bus 0, default is not (0)
default SB_HT_CHAIN_ON_BUS0=2

#only offset for SB chain?, default is yes(1)
default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0

#allow capable device use that above 4G
#default CONFIG_PCI_64BIT_PREF_MEM=1

##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xc8000
default DCACHE_RAM_SIZE=0x08000
default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
default CONFIG_USE_INIT=0

default CONFIG_AP_CODE_IN_CAR=0
default MEM_TRAIN_SEQ=1
default WAIT_BEFORE_CPUS_INIT=1

##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1

##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="l1_2pvv"
default MAINBOARD_VENDOR="NVIDIA"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80

###
### coreboot layout values
###

## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536

##
## Use a small 8K stack
##
default STACK_SIZE=0x2000

##
## Use a small 32K heap
##
default HEAP_SIZE=0x8000

##
## Only use the option table in a normal image
##
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )

##
## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00100000

##
## Load the payload from the ROM
##
default CONFIG_ROM_PAYLOAD = 1

#default CONFIG_COMPRESSED_PAYLOAD = 1

###
### Defaults of options that you may want to override in the target config file
###

##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"

##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0

##
## The Serial Console
##
default CONFIG_USE_PRINTK_IN_CAR=1

# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1

## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200

# Select the serial console base port
default TTYS0_BASE=0x3f8

# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3

##
### Select the coreboot loglevel
##
## EMERG      1   system is unusable
## ALERT      2   action must be taken immediately
## CRIT       3   critical conditions
## ERR        4   error conditions
## WARNING    5   warning conditions
## NOTICE     6   normal but significant condition
## INFO       7   informational
## DEBUG      8   debug-level messages
## SPEW       9   Way too many details

## Request this level of debugging output
default  DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default  MAXIMUM_CONSOLE_LOGLEVEL=8

##
## Select power on after power fail setting
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"

### End Options.lb
end