summaryrefslogtreecommitdiff
path: root/src/mainboard/nvidia/l1_2pvv/Kconfig
blob: 502da61dac3d202cb0da777953a6250e250aaf55 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
if BOARD_NVIDIA_L1_2PVV

config BOARD_SPECIFIC_OPTIONS # dummy
	def_bool y
	select ARCH_X86
	select CPU_AMD_SOCKET_F
	select DIMM_DDR2
	select DIMM_REGISTERED
	select NORTHBRIDGE_AMD_AMDK8
	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
	select SOUTHBRIDGE_NVIDIA_MCP55
	select SUPERIO_WINBOND_W83627EHG
	select HAVE_OPTION_TABLE
	select HAVE_BUS_CONFIG
	select HAVE_PIRQ_TABLE
	select HAVE_MP_TABLE
	select CACHE_AS_RAM
	select HAVE_HARD_RESET
	select LIFT_BSP_APIC_ID
	select K8_REV_F_SUPPORT
	select BOARD_ROMSIZE_KB_512

config MAINBOARD_DIR
	string
	default nvidia/l1_2pvv

config DCACHE_RAM_BASE
	hex
	default 0xc8000

config DCACHE_RAM_SIZE
	hex
	default 0x08000

config DCACHE_RAM_GLOBAL_VAR_SIZE
	hex
	default 0x01000

config APIC_ID_OFFSET
	hex
	default 0x10

config MEM_TRAIN_SEQ
	int
	default 1

config SB_HT_CHAIN_ON_BUS0
	int
	default 2

config MAINBOARD_PART_NUMBER
	string
	default "l1_2pvv"

config PCI_64BIT_PREF_MEM
	bool
	default n

config HW_MEM_HOLE_SIZEK
	hex
	default 0x100000

config MAX_CPUS
	int
	default 4

config MAX_PHYSICAL_CPUS
	int
	default 2

config HW_MEM_HOLE_SIZE_AUTO_INC
	bool
	default n

config HT_CHAIN_UNITID_BASE
	hex
	default 0x0

config HT_CHAIN_END_UNITID_BASE
	hex
	default 0x20

config SERIAL_CPU_INIT
	bool
	default n

config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
	hex
	default 0x1022

config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
	hex
	default 0x2b80

config IRQ_SLOT_COUNT
	int
	default 11

endif # BOARD_NVIDIA_L1_2PVV