path: root/src/mainboard/nvidia/l1_2pvv/Config.lb

##
## This file is part of the coreboot project.
##
## Copyright (C) 2007 AMD
## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
	default ROM_SECTION_SIZE   = FAILOVER_SIZE
	default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
else
    if USE_FALLBACK_IMAGE
	default ROM_SECTION_SIZE   = FALLBACK_SIZE
	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
    else
	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
	default ROM_SECTION_OFFSET = 0
    end
end

##
## Compute the start location and size size of
## The coreboot bootloader.
##
default PAYLOAD_SIZE             = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)

##
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )

##
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536

if USE_FAILOVER_IMAGE
	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
else
    if USE_FALLBACK_IMAGE
	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
    else
	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
    end
end

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o
#needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o

if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o

if HAVE_ACPI_TABLES
	object acpi_tables.o
	object fadt.o
	makerule dsdt.c
		depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
		action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
		action  "mv dsdt_lb.hex dsdt.c"
	end
	object ./dsdt.o

	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb

	if ACPI_SSDTX_NUM
	    makerule ssdt6.c
			depends "$(MAINBOARD)/dx/pci6.asl"
			action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci6.asl"
			action  "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex"
			action  "mv pci6.hex ssdt6.c"
	    end
	    object ./ssdt6.o
	    makerule ssdt5.c
			depends "$(MAINBOARD)/dx/pci5.asl"
			action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci5.asl"
			action  "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
			action  "mv pci5.hex ssdt5.c"
	    end
	    object ./ssdt5.o
	end
end

if USE_DCACHE_RAM

	if CONFIG_USE_INIT
		makerule ./cache_as_ram_auto.o
			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
		end
	else
		makerule ./cache_as_ram_auto.inc
			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
			action "perl -e 's/.rodata/.rom.data/g' -pi $@"
			action "perl -e 's/.text/.section .rom.text/g' -pi $@"
		end
	end

end

if USE_FAILOVER_IMAGE
else
    if CONFIG_AP_CODE_IN_CAR
	makerule ./apc_auto.o
		depends "$(MAINBOARD)/apc_auto.c option_table.h"
		action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
	end
	ldscript /arch/i386/init/ldscript_apc.lb
    end
end


##
## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
    if USE_FAILOVER_IMAGE
	mainboardinit cpu/x86/16bit/entry16.inc
	ldscript /cpu/x86/16bit/entry16.lds
    end
else
    if USE_FALLBACK_IMAGE
	mainboardinit cpu/x86/16bit/entry16.inc
	ldscript /cpu/x86/16bit/entry16.lds
    end
end

mainboardinit cpu/x86/32bit/entry32.inc

if USE_DCACHE_RAM
	if CONFIG_USE_INIT
		ldscript /cpu/x86/32bit/entry32.lds
	end

	if CONFIG_USE_INIT
		ldscript /cpu/amd/car/cache_as_ram.lds
	end
end


##
## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
    if USE_FAILOVER_IMAGE
	mainboardinit cpu/x86/16bit/reset16.inc
	ldscript /cpu/x86/16bit/reset16.lds
    else
	mainboardinit cpu/x86/32bit/reset32.inc
	ldscript /cpu/x86/32bit/reset32.lds
    end
else
    if USE_FALLBACK_IMAGE
	mainboardinit cpu/x86/16bit/reset16.inc
	ldscript /cpu/x86/16bit/reset16.lds
    else
	mainboardinit cpu/x86/32bit/reset32.inc
	ldscript /cpu/x86/32bit/reset32.lds
    end
end

##
## Include an id string (For safe flashing)
##
mainboardinit southbridge/nvidia/mcp55/id.inc
ldscript /southbridge/nvidia/mcp55/id.lds

##
## ROMSTRAP table for MCP55
##
if HAVE_FAILOVER_BOOT
    if USE_FAILOVER_IMAGE
	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
	ldscript /southbridge/nvidia/mcp55/romstrap.lds
    end
else
    if USE_FALLBACK_IMAGE
	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
	ldscript /southbridge/nvidia/mcp55/romstrap.lds
    end
end

if USE_DCACHE_RAM
	##
	## Setup Cache-As-Ram
	##
	mainboardinit cpu/amd/car/cache_as_ram.inc
end

###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if HAVE_FAILOVER_BOOT
    if USE_FAILOVER_IMAGE
	if USE_DCACHE_RAM
		ldscript /arch/i386/lib/failover_failover.lds
	end
    end
else
    if USE_FALLBACK_IMAGE
	if USE_DCACHE_RAM
		ldscript /arch/i386/lib/failover.lds
	end
    end
end

##
## Setup RAM
##
if USE_DCACHE_RAM

	if CONFIG_USE_INIT
		initobject cache_as_ram_auto.o
	else
		mainboardinit ./cache_as_ram_auto.inc
	end
end

##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
	config chip.h
end

chip northbridge/amd/amdk8/root_complex
	device apic_cluster 0 on
		chip cpu/amd/socket_F
			device apic 0 on end
		end
	end
	device pci_domain 0 on
		chip northbridge/amd/amdk8 #mc0
			device pci 18.0 on
				#  devices on link 0, link 0 == LDT 0
				chip southbridge/nvidia/mcp55
					device pci 0.0 on end   # HT
					device pci 1.0 on # LPC
						chip superio/winbond/w83627ehg
							device pnp 2e.0 off #  Floppy
					 			io 0x60 = 0x3f0
								irq 0x70 = 6
								drq 0x74 = 2
							end
							device pnp 2e.1 off #  Parallel Port
					 			io 0x60 = 0x378
								irq 0x70 = 7
							end
							device pnp 2e.2 on #  Com1
					 			io 0x60 = 0x3f8
								irq 0x70 = 4
							end
							device pnp 2e.3 off #  Com2
					 			io 0x60 = 0x2f8
								irq 0x70 = 3
							end
							device pnp 2e.5 on #  Keyboard
					 			io 0x60 = 0x60
					 			io 0x62 = 0x64
								irq 0x70 = 1
								irq 0x72 = 12
							end
							device pnp 2e.6 off  # SFI
					 			io 0x62 = 0x100
							end
							device pnp 2e.7 off #  GPIO_GAME_MIDI
								io 0x60 = 0x220
								io 0x62 = 0x300
								irq 0x70 = 9
							end
							device pnp 2e.8 off end #  WDTO_PLED
							device pnp 2e.9 off end #  GPIO_SUSLED
							device pnp 2e.a off end #  ACPI
							device pnp 2e.b on #  HW Monitor
 					 			io 0x60 = 0x290
								irq 0x70 = 5
							end
						end
					end
					device pci 1.1 on # SM 0
						chip drivers/generic/generic #dimm 0-0-0
							device i2c 50 on end
						end
						chip drivers/generic/generic #dimm 0-0-1
							device i2c 51 on end
						end
						chip drivers/generic/generic #dimm 0-1-0
							device i2c 52 on end
						end
						chip drivers/generic/generic #dimm 0-1-1
							device i2c 53 on end
						end
						chip drivers/generic/generic #dimm 1-0-0
							device i2c 54 on end
						end
						chip drivers/generic/generic #dimm 1-0-1
							device i2c 55 on end
						end
						chip drivers/generic/generic #dimm 1-1-0
							device i2c 56 on end
						end
						chip drivers/generic/generic #dimm 1-1-1
							device i2c 57 on end
						end
					end # SM
					device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
#						chip drivers/generic/generic #PCIXA Slot1
#							device i2c 50 on end
#						end
#						chip drivers/generic/generic #PCIXB Slot1
#							device i2c 51 on end
#						end
#						chip drivers/generic/generic #PCIXB Slot2
#							device i2c 52 on end
#						end
#						chip drivers/generic/generic #PCI Slot1
#							device i2c 53 on end
#						end
#						chip drivers/generic/generic #Master MCP55 PCI-E
#							device i2c 54 on end
#						end
#						chip drivers/generic/generic #Slave MCP55 PCI-E
#							device i2c 55 on end
#						end
						chip drivers/generic/generic #MAC EEPROM
							device i2c 51 on end
						end

					end # SM
					device pci 2.0 on end # USB 1.1
					device pci 2.1 on end # USB 2
					device pci 4.0 on end # IDE
					device pci 5.0 on end # SATA 0
					device pci 5.1 on end # SATA 1
					device pci 5.2 on end # SATA 2
					device pci 6.0 on end # PCI
					device pci 6.1 on end # AZA
					device pci 8.0 on end # NIC
					device pci 9.0 on end # NIC
		       			device pci a.0 on end # PCI E 5
		       			device pci b.0 off end # PCI E 4
					device pci c.0 off end # PCI E 3
					device pci d.0 on end # PCI E 2
					device pci e.0 off end # PCI E 1
		       			device pci f.0 on end # PCI E 0
					register "ide0_enable" = "1"
					register "sata0_enable" = "1"
					register "sata1_enable" = "1"
					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
					register "mac_eeprom_addr" = "0x51"
				end
			end #  device pci 18.0
			device pci 18.0 on end # Link 1
			device pci 18.0 on
				#  devices on link 2, link 2 == LDT 2
				chip southbridge/nvidia/mcp55
					device pci 0.0 on end   # HT
					device pci 1.0 on end  # LPC
					device pci 1.1 on end # SM 0
					device pci 2.0 off end # USB 1.1
					device pci 2.1 off end # USB 2
					device pci 4.0 off end # IDE
					device pci 5.0 on end # SATA 0
					device pci 5.1 on end # SATA 1
					device pci 5.2 on end # SATA 2
					device pci 6.0 off end # PCI
					device pci 6.1 off end # AZA
					device pci 8.0 on end # NIC
					device pci 9.0 on end # NIC
		       			device pci a.0 on end # PCI E 5
		       			device pci b.0 off end # PCI E 4
					device pci c.0 off end # PCI E 3
					device pci d.0 on end # PCI E 2
					device pci e.0 on end # PCI E 1
		       			device pci f.0 on end # PCI E 0
					register "ide0_enable" = "1"
					register "sata0_enable" = "1"
					register "sata1_enable" = "1"
					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
					register "mac_eeprom_addr" = "0x51"
				end
			end # device pci 18.0
			device pci 18.1 on end
			device pci 18.2 on end
			device pci 18.3 on end
		end # mc0

	end # PCI domain

#       chip drivers/generic/debug
#		device pnp 0.0 off end # chip name
#		device pnp 0.1 on end # pci_regs_all
#		device pnp 0.2 on end # mem
#		device pnp 0.3 off end # cpuid
#		device pnp 0.4 on end # smbus_regs_all
#		device pnp 0.5 off end # dual core msr
#		device pnp 0.6 off end # cache size
#		device pnp 0.7 off end # tsc
#		device pnp 0.8 off  end # io
#		device pnp 0.9 off end # io
#       end
end #root_complex