blob: 3e67f6377681f504190ac761b91a33fd82242632 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* DefinitionBlock Statement */
#include <acpi/acpi.h>
DefinitionBlock (
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */
#include <acpi/dsdt_top.asl>
#include <arch/x86/acpi/debug.asl> /* Include global debug methods if needed */
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
#include "acpi/sleep.asl"
Scope(\_SB) {
/* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl>
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
#include "acpi/routing.asl"
Device(PCI0) {
/* Describe the AMD Northbridge */
#include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
/* Describe the AMD Fusion Controller Hub Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
}
/* Describe PCI INT[A-H] for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
/* Describe USB for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/usb.asl>
} /* End Scope(_SB) */
/* Describe SMBUS for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
/* Define the General Purpose Events for the platform */
#include "acpi/gpe.asl"
/* Define the Thermal zones and methods for the platform */
#include "acpi/thermal.asl"
}
/* End of ASL file */
|
