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#
# This file is part of the coreboot project.
#
# Copyright (C) 2007-2008 coresystems GmbH
# 2012 secunet Security Networks AG
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; version 2 of
# the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# -----------------------------------------------------------------
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 240 r 0 unused
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 2 r 0 unused?
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 6 debug_level
#399 1 r 0 unused
#400 8 r 0 reserved for century byte
# coreboot config options: southbridge
408 1 e 10 sata_mode
409 2 e 7 power_on_after_fail
# coreboot config options: EC
411 1 e 9 first_battery
412 1 e 1 bluetooth
413 1 e 1 wwan
414 1 e 1 wlan
415 1 e 1 trackpoint
416 8 h 0 volume
424 1 e 1 fn_ctrl_swap
425 1 e 1 sticky_fn
426 1 e 1 power_management_beeps
427 1 e 1 low_battery_beep
428 1 e 1 uwb
# coreboot config options: bootloader
432 512 s 0 boot_devices
944 8 h 0 boot_default
# coreboot config options: northbridge
952 2 e 12 hybrid_graphics_mode
954 4 e 11 gfx_uma_size
# coreboot config options: check sums
984 16 h 0 check_sum
#1000 24 r 0 unused
# RAM initialization internal data
1024 128 r 0 read_training_results
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
8 0 No
8 1 Yes
9 0 Secondary
9 1 Primary
10 0 AHCI
10 1 Compatible
11 4 32M
11 5 48M
11 6 64M
11 7 128M
11 8 256M
11 9 96M
11 10 160M
11 11 224M
11 12 352M
12 0 Integrated Only
12 1 Discrete Only
12 2 Switchable
# -----------------------------------------------------------------
checksums
checksum 392 983 984
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