1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
|
## SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/skylake
# Enable deep Sx states
register "deep_s5_enable_ac" = "1"
register "deep_s5_enable_dc" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
register "eist_enable" = "1"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "gpe0_dw0" = "GPP_G"
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
register "PmConfigSlpS3MinAssert" = "0x02"
# SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
register "PmConfigSlpS4MinAssert" = "0x04"
# SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
register "PmConfigSlpSusMinAssert" = "0x03"
# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
register "PmConfigSlpAMinAssert" = "0x03"
# PL2 override 65W
register "power_limits_config" = "{
.tdp_pl2_override = 65,
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
}"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
#+----------------+-------+-------+-------+-------+
#| Psi1Threshold | 20A | 20A | 20A | 20A |
#| Psi2Threshold | 4A | 5A | 5A | 5A |
#| Psi3Threshold | 1A | 1A | 1A | 1A |
#| Psi3Enable | 1 | 1 | 1 | 1 |
#| Psi4Enable | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 |
#| IccMax | 11A | 66A | 48A | 48A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#| AcLoadline | 3.9 | 2.1 | 3.1 | 3.1 |
#| DcLoadline | 3.9 | 2.1 | 3.1 | 3.1 |
#+----------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(4),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(11),
.voltage_limit = 1520,
.ac_loadline = 390,
.dc_loadline = 390,
}"
register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(66),
.voltage_limit = 1520,
.ac_loadline = 210,
.dc_loadline = 210,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(48),
.voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
.psi2threshold = VR_CFG_AMP(5),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(48),
.voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,
}"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
device cpu_cluster 0 on end
device domain 0 on
subsystemid 0x17aa 0x30d0 inherit
device ref igpu on
register "PrimaryDisplay" = "Display_iGFX"
end
device ref sa_thermal on end
device ref gmm on end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC0), // Front Port 1
[1] = USB2_PORT_MID(OC0), // Front Port 2
[2] = USB2_PORT_MID(OC1), // Rear Port 3
[3] = USB2_PORT_MID(OC2), // Rear Port 4
[4] = USB2_PORT_MID(OC3), // Rear Port 5
[5] = USB2_PORT_MID(OC4), // Rear Port 6
[6] = USB2_PORT_MID(OC1), // Internal header
[8] = USB2_PORT_SHORT(OC_SKIP), // M.2 2230
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), // Front Port 1
[1] = USB3_PORT_DEFAULT(OC0), // Front Port 2
[2] = USB3_PORT_DEFAULT(OC3), // Rear Port 3
[3] = USB3_PORT_DEFAULT(OC3), // Rear Port 4
[4] = USB3_PORT_DEFAULT(OC1), // Rear Port 5
[5] = USB3_PORT_DEFAULT(OC1), // Rear Port 6
}"
end
device ref thermal on end
device ref heci1 on end
device ref sata on
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{
[0] = 1,
[1] = 1,
[2] = 1,
[3] = 1,
[4] = 1,
}"
register "SataPortsHotPlug" = "{
[0] = 1,
[1] = 1,
}"
end
device ref pcie_rp17 on # M.2 2280 / 2242 - SSD
register "PcieRpEnable[16]" = "1"
register "PcieRpClkReqSupport[16]" = "1"
register "PcieRpClkReqNumber[16]" = "1"
register "PcieRpAdvancedErrorReporting[16]" = "1"
register "PcieRpLtrEnable[16]" = "1"
register "PcieRpClkSrcNumber[16]" = "7"
register "PcieRpHotPlug[16]" = "1"
end
device ref pcie_rp7 on # M.2 2230 - WLAN
register "PcieRpEnable[6]" = "1"
register "PcieRpClkReqSupport[6]" = "1"
register "PcieRpClkReqNumber[6]" = "11"
register "PcieRpAdvancedErrorReporting[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpClkSrcNumber[6]" = "1"
register "PcieRpHotPlug[6]" = "1"
chip drivers/wifi/generic
register "wake" = "GPE0_PCI_EXP"
device generic 0 on end
end
end
device ref lpc_espi on
# Set LPC Serial IRQ mode
register "serirq_mode" = "SERIRQ_CONTINUOUS"
chip superio/nuvoton/nct6687d
device pnp 2e.1 off end # Parallel port
device pnp 2e.2 on # COM1 - optional module
io 0x60 = 0x3f8
irq 0x70 = 3
end
device pnp 2e.3 off end # COM2, IR
device pnp 2e.5 off end # Keyboard
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GPIO0-7
device pnp 2e.8 off end # P80 UART
device pnp 2e.9 off end # GPIO8-9, GPIO1-8 AF
device pnp 2e.a on # ACPI
io 0x60 = 0xa10
end
device pnp 2e.b on # EC
io 0x60 = 0xa20
end
device pnp 2e.c off end # RTC
device pnp 2e.d off end # Deep Sleep
device pnp 2e.e on # TACH/PWM assignment
irq 0xe4 = 0x10
irq 0xe5 = 0x09
end
device pnp 2e.f off end # Function register
end
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device ref hda on end
device ref smbus on end
device ref gbe on end
end
end
|
