1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "agesawrapper.h"
#include <console/console.h>
#include <cpu/amd/amdfam14.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <southbridge/amd/cimx/sb800/sb_cimx.h>
/**
* Global variables for mainboard layouts. These are shared by irqtable,
* mptable and acpi_tables where busnum is default.
*/
u8 bus_isa;
u8 bus_sb800[6];
u32 apicid_sb800;
/**
* Here you only need to set value in pci1234 for HT-IO that could be
* installed or not. You may need to preset pci1234 for HTIO board,
* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
*/
u32 pci1234x[] = {
0x0000ff0,
};
u32 bus_type[256];
u32 sbdn_sb800;
static u32 get_bus_conf_done = 0;
#if CONFIG_HAVE_ACPI_RESUME
extern u8 acpi_slp_type;
#endif /* CONFIG_HAVE_ACPI_RESUME */
void get_bus_conf(void)
{
u32 apicid_base;
u32 status;
device_t dev;
int i, j;
/* Be sure func is called exactly once */
if (get_bus_conf_done == 1)
return;
get_bus_conf_done = 1;
/*
* This is the call to AmdInitLate. It is really in the wrong place,
* conceptually, but functionally within the coreboot model, this is the
* best place to make the call. The logically correct place to call
* AmdInitLate is after PCI scan is done, after the decision about S3
* resume is made, and before the system tables are written into RAM. The
* routine that is
* responsible for writing the tables is "write_tables", called near the
* end of "main". There is no platform specific entry point between the S3
* resume decision point and the call to "write_tables", and the next
* platform specific entry points are the calls to the ACPI table write
* functions. The first of ose would seem to be the right place, but other
* table write
* functions, e.g. the PIRQ table write function, are called before the
* ACPI tables are written. This routine is called at the beginning of each
* of the write functions called prior to the ACPI write functions, so this
* becomes the best place for this call.
*/
#if CONFIG_HAVE_ACPI_RESUME
if (acpi_slp_type != 3) {
status = agesawrapper_amdinitlate();
if(status)
printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
status = agesawrapper_amdS3Save();
if(status)
printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status);
}
#else
status = agesawrapper_amdinitlate();
if(status)
printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
#endif /* CONFIG_HAVE_ACPI_RESUME */
sbdn_sb800 = 0;
memset(bus_sb800, 0, sizeof(bus_sb800));
for (i = 0; i < 256; i++) {
bus_type[i] = 0; /* default ISA bus. */
}
bus_type[0] = 1; /* pci */
// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
/* sb800 */
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
if (dev) {
bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
for (j = bus_sb800[1]; j < bus_isa; j++)
bus_type[j] = 1;
}
for (i = 0; i < 4; i++) {
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
if (dev) {
bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
}
for (j = bus_sb800[2]; j < bus_isa; j++)
bus_type[j] = 1;
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
apicid_base = CONFIG_MAX_CPUS;
apicid_sb800 = apicid_base;
#if CONFIG_AMD_SB_CIMX
sb_Late_Post();
#endif /* CONFIG_AMD_SB_CIMX */
}
|
