1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
|
/*
* This file is part of the coreboot project.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <PlatformMemoryConfiguration.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* (PCIe port, Lanes 4, PCI Device Number 4, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER(PortEnabled,
ChannelTypeExt6db,
4,
HotplugDisabled,
PcieGen2,
PcieGen2,
AspmL0sL1,
46)
},
/* (PCIe port, Lanes 5, PCI Device Number 5, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER(PortEnabled,
ChannelTypeExt6db,
5,
HotplugDisabled,
PcieGen2,
PcieGen2,
AspmL0sL1,
46)
},
/* (PCIe port, Lanes 6, PCI Device Number 6, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER(PortEnabled,
ChannelTypeExt6db,
6,
HotplugDisabled,
PcieGen2,
PcieGen2,
AspmL0sL1,
46)
},
/* (PCIe port, Lanes 7, PCI Device Number 7, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER(PortDisabled,
ChannelTypeExt6db,
7,
HotplugDisabled,
PcieGen2,
PcieGen2,
AspmL0sL1,
0)
},
/* (PCIe port, Lanes 8, PCI Device Number 8, ...) */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER(PortEnabled,
ChannelTypeExt6db,
8,
HotplugDisabled,
PcieGen2,
PcieGen2,
AspmL0sL1,
0)
}
};
static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* (DDI interface Lanes 8:11, DdA, ...) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) */
{ConnectorTypeLvds, Aux1, Hdp1}
},
/* (DDI interface Lanes 12:15, DdB, ...) */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) */
{ConnectorTypeDP, Aux2, Hdp2}
}
};
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
.Flags = DESCRIPTOR_TERMINATE_LIST,
.SocketId = 0,
.PciePortList = PortList,
.DdiLinkList = DdiList,
};
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
InitEarly->GnbConfig.PsppPolicy = 0;
}
/**
* @brief Customer Overides Memory Table
*
* Platform Specific Overriding Table allows IBV/OEM to pass in platform
* information to AGESA
* (e.g. MemClk routing, the number of DIMM slots per channel,...).
* If PlatformSpecificTable is populated, AGESA will base its settings on the
* data from the table. Otherwise, it will use its default conservative settings.
*/
static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
PSO_END
};
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
{
InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
}
|
