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FLASH@0xff000000 0x1000000 {
SI_ALL@0x0 0x381000 {
SI_DESC@0x0 0x1000
SI_EC@0x1000 0x80000
SI_ME@0x81000 0x300000
}
SI_BIOS@0x381000 0xc7f000 {
RW_LEGACY(CBFS)@0x0 0x100000
RW_SECTION_A@0x100000 0x3a4800 {
VBLOCK_A@0x0 0x2000
FW_MAIN_A(CBFS)@0x2000 0x2127c0
RW_FWID_A@0x2147c0 0x40
ME_RW_A(CBFS)@0x214800 0x190000
}
RW_SECTION_B@0x4a4800 0x3a4800 {
VBLOCK_B@0x0 0x2000
FW_MAIN_B(CBFS)@0x2000 0x2127c0
RW_FWID_B@0x2147c0 0x40
ME_RW_B(CBFS)@0x214800 0x190000
}
RW_MISC@0x849000 0x36000 {
UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x20000
}
RW_ELOG(PRESERVE)@0x30000 0x1000
RW_SHARED@0x31000 0x1000 {
SHARED_DATA@0x0 0x1000
}
RW_VPD(PRESERVE)@0x32000 0x2000
RW_NVRAM(PRESERVE)@0x34000 0x2000
}
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO@0x87f000 0x400000 {
RO_VPD(PRESERVE)@0x0 0x4000
RO_SECTION@0x4000 0x3fc000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0x3000
COREBOOT(CBFS)@0x4000 0x3f8000
}
}
}
}
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