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##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 - 2017 Intel Corporation.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_INTEL_HARCUVAR
config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_INTEL_DENVERTON_NS
select BOARD_ROMSIZE_KB_16384
select HAVE_ACPI_TABLES
config MAINBOARD_DIR
string
default intel/harcuvar
config MAINBOARD_PART_NUMBER
string
default "Harcuvar CRB"
config MAINBOARD_VENDOR
string
default "Intel"
config ENABLE_FSP_MEMORY_DOWN
bool "Enable Memory Down"
default n
help
Select this option to enable Memory Down function.
config SPD_LOC
depends on ENABLE_FSP_MEMORY_DOWN
hex "SPD binary location in cbfs"
default 0xfffdf000
help
Location of SPD binary for memory down function.
endif # BOARD_INTEL_HARCUVAR
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