1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
|
chip soc/intel/apollolake
register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
# Disable unused clkreq of PCIe root ports
register "pcie_rp_clkreq_pin[1]" = "3" # wifi/bt
register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
register "prt0_gpio" = "GPIO_163"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "GPIO_186"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3.
# [14:8] steps of delay for HS400, each 125ps.
# [6:0] steps of delay for SDR104/HS200, each 125ps.
register "emmc_tx_data_cntl1" = "0x0C3A"
# EMMC TX DATA Delay 2
# Refer to EDS-Vol2-22.3.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_tx_data_cntl2" = "0x28272929"
# EMMC RX CMD/DATA Delay 1
# Refer to EDS-Vol2-22.3.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_rx_cmd_data_cntl1" = "0x003B263B"
# EMMC RX CMD/DATA Delay 2
# Refer to EDS-Vol2-22.3.
# [17:16] stands for Rx Clock before Output Buffer
# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
# [6:0] steps of delay for HS200, each 125ps.
register "emmc_rx_cmd_data_cntl2" = "0x10008"
register "emmc_rx_strobe_cntl" = "0x0a0a"
register "emmc_tx_cmd_cntl" = "0x1305"
# Enable DPTF
register "dptf_enable" = "1"
# PL1 override: 7.5W setting gives a run-time 6W actual
# Set RAPL PL2 to 15W.
register "power_limits_config" = "{
.tdp_pl1_override = 7,
.tdp_pl2_override = 15,
}"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
register "hdaudio_pwr_gate_enable" = "1"
register "hdaudio_bios_config_lockdown" = "1"
# Enable lpss s0ix
register "lpss_s0ix_enable" = "1"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed. This sets the PMC register
# GPE_CFG fields.
#PMC_GPE_NW_63_32 - 03
#PMC_GPE_N_95_64 - 08
#PMC_GPE_NW_31_0 - 02
register "gpe0_dw1" = "PMC_GPE_NW_63_32"
register "gpe0_dw2" = "PMC_GPE_N_95_64"
register "gpe0_dw3" = "PMC_GPE_NW_31_0"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
}"
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
register "pnp_settings" = "PNP_PERF_POWER"
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF
device pci 00.2 on end # - NPK
device pci 02.0 on end # - Gen
device pci 03.0 on end # - Iunit
device pci 0c.0 on end # - CNVi
device pci 0d.0 on end # - P2SB
device pci 0d.1 on end # - PMC
device pci 0d.2 on end # - SPI
device pci 0d.3 on end # - Shared SRAM
device pci 0e.0 on # - Audio
chip drivers/generic/max98357a
register "hid" = ""MX98357A""
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_160)"
register "sdmode_delay" = "5"
device generic 0 on end
end
end
device pci 0f.0 on end # - Heci1
device pci 0f.1 on end # - Heci2
device pci 0f.2 on end # - Heci3
device pci 11.0 off end # - ISH
device pci 12.0 on # - SATA
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
end
device pci 13.0 off end # - PCIe-A 0 Slot 1
device pci 13.1 off end # - PCIe-A 1
device pci 13.2 off end # - PCIe-A 2 Onboard Lan
device pci 13.3 off end # - PCIe-A 3
device pci 14.0 off end # - PCIe-B 0 Slot2
device pci 14.1 on end # - PCIe-B 1 Onboard M2 Slot(Wifi/BT)
device pci 15.0 on end # - XHCI
device pci 15.1 off end # - XDCI
device pci 16.0 on # - I2C 0
chip drivers/i2c/da7219
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_20_IRQ)"
register "btn_cfg" = "50"
register "mic_det_thr" = "500"
register "jack_ins_deb" = "20"
register "jack_det_rate" = ""32ms_64ms""
register "jack_rem_deb" = "1"
register "a_d_btn_thr" = "0xa"
register "d_b_btn_thr" = "0x16"
register "b_c_btn_thr" = "0x21"
register "c_mic_btn_thr" = "0x3e"
register "btn_avg" = "4"
register "adc_1bit_rpt" = "1"
register "micbias_lvl" = "2600"
register "mic_amp_in_sel" = ""diff""
device i2c 1a on end
end
end
device pci 16.1 off end # - I2C 1
device pci 16.2 off end # - I2C 2
device pci 16.3 off end # - I2C 3
device pci 17.0 on
chip drivers/i2c/hid
register "generic.hid" = ""ALPS0001""
register "generic.desc" = ""Touchpad""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
register "hid_desc_reg_offset" = "0x1"
device i2c 2C on end
end
end # I2C 4
device pci 17.1 off end # - I2C 5
device pci 17.2 off end # - I2C 6
device pci 17.3 on end # - I2C 7
device pci 18.0 on end # - UART 0
device pci 18.1 off end # - UART 1
device pci 18.2 on end # - UART 2
device pci 18.3 off end # - UART 3
device pci 19.0 on end # - SPI 0
device pci 19.1 on end # - SPI 1
device pci 19.2 on end # - SPI 2
device pci 1a.0 on end # - PWM
device pci 1b.0 on end # - SDCARD
device pci 1c.0 on end # - eMMC
device pci 1d.0 on end # - UFS
device pci 1e.0 off end # - SDIO
device pci 1f.0 on # - LPC
chip drivers/pc80/tpm
register "irq_polarity" = "2"
device pnp 0c31.0 on
irq 0x70 = 10
end
end
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end
device pci 1f.1 on end # - SMBUS
end
end
|
