blob: a19a676804dd590caa1dd88dfc0327ad4dba7d0f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
chip soc/intel/fsp_baytrail
#### ACPI Register Settings ####
register "fadt_pm_profile" = "PM_MOBILE"
register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
#### FSP register settings ####
register "PcdSataMode" = "SATA_MODE_AHCI"
register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
register "PcdMrcInitTsegSize" = "TSEG_SIZE_8_MB"
register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
register "PcdGttSize" = "GTT_SIZE_DEFAULT"
register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # 8086 0F00 - SoC router
device pci 02.0 on end # 8086 0F31 - GFX
device pci 03.0 off end # 8086 0F38 - MIPI - camera interface
device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time
device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins)
device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins)
device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
device pci 15.0 off end # 8086 0F28 - LP Engine Audio
device pci 16.0 off end # 8086 0F37 - OTG controller
device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
device pci 18.0 on end # 8086 0F40 - SIO - DMA
device pci 18.1 on end # 8086 0F41 - I2C Port 1
device pci 18.2 on end # 8086 0F42 - I2C Port 2
device pci 18.3 on end # 8086 0F43 - I2C Port 3
device pci 18.4 on end # 8086 0F44 - I2C Port 4
device pci 18.5 on end # 8086 0F45 - I2C Port 5
device pci 18.6 on end # 8086 0F46 - I2C Port 6
device pci 18.7 on end # 8086 0F47 - I2C Port 7
device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine
device pci 1b.0 on end # 8086 0F04 - HD Audio
device pci 1c.0 on end # 8086 0F48 - PCIe Root Port 1 (x4 slot)
device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot)
device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (front x1 slot)
device pci 1c.3 on end # 8086 0F4E - PCIe Root Port 4 (rear x1 slot)
device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
device pci 1e.0 on end # 8086 0F06 - SIO - DMA
device pci 1e.1 on end # 8086 0F08 - PWM 1
device pci 1e.2 on end # 8086 0F09 - PWM 2
device pci 1e.3 on end # 8086 0F0A - HSUART 1
device pci 1e.4 on end # 8086 0F0C - HSUART 2
device pci 1e.5 on end # 8086 0F0E - SPI
device pci 1f.0 on end # 8086 0F1C - LPC bridge
device pci 1f.3 on end # 8086 0F12 - SMBus 0
end
end
|
