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|
chip soc/intel/alderlake
device cpu_cluster 0 on
device lapic 0 on end
end
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "pmc_gpe0_dw0" = "GPP_B"
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
# FSP configuration
register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A port 1
register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # Type-A port 2
register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WLAN
# Enable CNVi Bluetooth
register "CnviBtCore" = "true"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
#Enable PCH PCIE RP 4 using CLK 5
register "pch_pcie_rp[PCH_RP(4)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
.PcieRpL1Substates = L1_SS_L1_2,
}"
# Enable PCH PCIE RP 5 using CLK 2
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
.PcieRpL1Substates = L1_SS_L1_2,
}"
# Enable PCH PCIE RP 9 using CLK 3
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
.PcieRpL1Substates = L1_SS_L1_2,
}"
#Enable PCH PCIE RP 10 using CLK 1
register "pch_pcie_rp[PCH_RP(10)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
.PcieRpL1Substates = L1_SS_L1_2,
}"
# Hybrid storage mode
register "HybridStorageMode" = "1"
# Enable CPU PCIE RP 1 using CLK 0
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_req = 0,
.clk_src = 0,
}"
# Enable EDP in PortA
register "DdiPortAConfig" = "1"
# Enable HDMI in Port B
register "ddi_ports_config" = "{
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
# TCSS USB3
register "TcssAuxOri" = "0"
register "s0ix_enable" = "1"
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
}"
register "SerialIoGSpiMode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoPci,
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
}"
register "SerialIoGSpiCsMode" = "{
[PchSerialIoIndexGSPI0] = 0,
[PchSerialIoIndexGSPI1] = 0,
[PchSerialIoIndexGSPI2] = 0,
[PchSerialIoIndexGSPI3] = 0,
}"
register "SerialIoGSpiCsState" = "{
[PchSerialIoIndexGSPI0] = 0,
[PchSerialIoIndexGSPI1] = 0,
[PchSerialIoIndexGSPI2] = 0,
[PchSerialIoIndexGSPI3] = 0,
}"
register "SerialIoUartMode" = "{
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
# HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
register "PchHdaIDispCodecEnable" = "1"
# Intel Common SoC Config
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
},
}"
device domain 0 on
device ref pcie5 on end
device ref igpu on end
device ref dtt on end
device ref ipu on end
device ref pcie4_0 on end
device ref pcie4_1 on end
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp1 on end
device ref tcss_xhci on end
device ref tcss_dma0 on end
device ref xhci on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port10 on end
end
end
end
end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref i2c0 on end
device ref i2c1 on end
device ref i2c2 on end
device ref i2c3 on end
device ref heci1 on end
device ref sata on end
device ref i2c5 on end
device ref pcie_rp1 on end
device ref pcie_rp3 on end # W/A to FSP issue
device ref pcie_rp4 on end # W/A to FSP issue
device ref pcie_rp5 on end
device ref pcie_rp6 on end
device ref pcie_rp8 on end
device ref pcie_rp9 on end
device ref pcie_rp10 on end
device ref uart0 on end
device ref gspi0 on end
device ref p2sb on end
device ref hda on
chip drivers/intel/soundwire
device generic 0 on
chip drivers/soundwire/alc711
# SoundWire Link 0 ID 1
register "desc" = ""Headset Codec""
device generic 0.1 on end
end
end
end
end
device ref smbus on end
end
end
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