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##
## This file is part of the coreboot project.
##
##
## SPDX-License-Identifier: GPL-2.0-only
if BOARD_GOOGLE_VEYRON_RIALTO
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_4096
select COMMON_CBFS_SPI_WRAPPER
select MAINBOARD_HAS_CHROMEOS
select SOC_ROCKCHIP_RK3288
select SPI_FLASH
select SPI_FLASH_GIGADEVICE
select SPI_FLASH_WINBOND
select MAINBOARD_HAS_I2C_TPM_GENERIC
select MAINBOARD_HAS_TPM1
config VBOOT
select VBOOT_VBNV_FLASH
config MAINBOARD_DIR
string
default "google/veyron_rialto"
config MAINBOARD_PART_NUMBER
string
default "Veyron_Rialto"
config BOOT_DEVICE_SPI_FLASH_BUS
int
default 2
config DRIVER_TPM_I2C_BUS
hex
default 0x1
config DRIVER_TPM_I2C_ADDR
hex
default 0x20
config CONSOLE_SERIAL_UART_ADDRESS
hex
depends on DRIVERS_UART
default 0xFF690000
config PMIC_BUS
int
default 0
endif # BOARD_GOOGLE_VEYRON_RIALTO
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