1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <string.h>
#include <bootmode.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include <ec/quanta/it8518/ec.h>
#if ENV_RAMSTAGE
#include <boot/coreboot_tables.h>
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
/* Write Protect: GPIO7 */
{7, ACTIVE_LOW, !get_write_protect_state(), "write protect"},
/* Lid Switch: Virtual switch */
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
/* Power Button: Virtual switch */
/* Hard-code value to de-asserted */
{-1, ACTIVE_HIGH, 0, "power"},
/* Was VGA Option ROM loaded? */
/* -1 indicates that this is a pseudo GPIO */
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
/* EC is in RW mode when it isn't in recovery mode. */
{-1, ACTIVE_HIGH, !get_recovery_mode_switch(), "ec_in_rw"}
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
#endif
int get_write_protect_state(void)
{
return !get_gpio(7);
}
int get_lid_switch(void)
{
/* hard-code to open */
return 1;
}
/*
* The recovery-switch is virtual on Stout and is handled via the EC.
* Stout recovery mode is only valid if RTC_PWR_STS is set and the EC
* indicated the recovery keys were pressed. We use a global flag for
* rec_mode to be used after RTC_POWER_STS has been cleared. This function
* is complicated by romstage support, which can't use a global variable.
* Note, rec_mode is the only time the EC is in RO mode, otherwise, RW.
*/
int get_recovery_mode_switch(void)
{
#ifdef __PRE_RAM__
pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
#else
static int ec_in_rec_mode = 0;
static int ec_rec_flag_good = 0;
struct device *dev = pcidev_on_root(0x1f, 0);
#endif
u8 ec_status = ec_read(EC_STATUS_REG);
u8 reg8 = pci_read_config8(dev, GEN_PMCON_3);
printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n",
__func__, ec_status, reg8 & RTC_BATTERY_DEAD);
#ifdef __PRE_RAM__
return (((reg8 & RTC_BATTERY_DEAD) != 0) &&
((ec_status & 0x3) == EC_IN_RECOVERY_MODE));
#else
if (!ec_rec_flag_good) {
ec_in_rec_mode = (((reg8 & RTC_BATTERY_DEAD) != 0) &&
((ec_status & 0x3) == EC_IN_RECOVERY_MODE));
ec_rec_flag_good = 1;
}
return ec_in_rec_mode;
#endif
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AL(7, CROS_GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
|
