1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
|
chip soc/intel/meteorlake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1
register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-A Port A0
register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C3
register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-A Port A4
register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-A Port A1
register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" # Type-A Port A2
register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A3
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type-A Port A0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type-A Port A1
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)"
register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)"
register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)"
# Enable Display Port Configuration
register "ddi_ports_config" = "{
[DDI_PORT_1] = DDI_ENABLE_HPD,
[DDI_PORT_2] = DDI_ENABLE_HPD,
[DDI_PORT_3] = DDI_ENABLE_HPD,
[DDI_PORT_4] = DDI_ENABLE_HPD,
}"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
}"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C4 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[4] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 600,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
},
}"
register "psys_pmax_watts" = "180"
# As per doc 640982, Intel MTL-U 28W CPU supports FVM on GT and SA
# The ICC Limit is represented in 1/4 A increments, i.e., a value of 400 = 100A
# For GT VR configuration
register "enable_fast_vmode[VR_DOMAIN_GT]" = "1"
register "cep_enable[VR_DOMAIN_IA]" = "1"
register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "216" # 54A
# For SA VR configuration
register "enable_fast_vmode[VR_DOMAIN_SA]" = "1"
register "cep_enable[VR_DOMAIN_SA]" = "1"
register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "108" # 27A
device domain 0 on
device ref dtt on
chip drivers/intel/dptf
device generic 0 alias dptf_policy on end
end
end
device ref pcie_rp5 on
# Enable WLAN Card PCIE 5 using clk 5
register "pcie_rp[PCH_RP(5)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip drivers/wifi/generic
register "wake" = "GPE0_DW1_05" # GPP_E05
register "add_acpi_dma_property" = "true"
device pci 00.0 on end
end
end #PCIE5 WLAN card
device ref pcie_rp7 on
# Enable LAN1 Card PCIE 7 using clk 2
register "pcie_rp[PCH_RP(7)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip drivers/net
register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW0_01" # GPP_D01
register "device_index" = "1"
register "add_acpi_dma_property" = "true"
device pci 00.0 on end
end
end # PCIE7 LAN1 card
device ref pcie_rp10 on
# Enable LAN0 Card PCIE 10 using clk 8
register "pcie_rp[PCH_RP(10)]" = "{
.clk_src = 8,
.clk_req = 8,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip drivers/net
register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_04" # GPP_E04
register "device_index" = "0"
register "add_acpi_dma_property" = "true"
device pci 00.0 on end
end
end # PCIE10 LAN0 card
device ref pcie_rp11 on
# Enable SSD Card PCIE 11 using clk 7
register "pcie_rp[PCH_RP(11)]" = "{
.clk_src = 7,
.clk_req = 7,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end # PCIE11 SSD card
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp1 on end
device ref tbt_pcie_rp2 on end
device ref tbt_pcie_rp3 on end
device ref tcss_xhci on
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C0""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))"
device ref tcss_usb3_port0 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
device ref tcss_usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C2""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(3, 1))"
device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C3""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
device ref tcss_usb3_port3 on end
end
end
end
end
device ref tcss_dma0 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
use tcss_usb3_port0 as dfp[0].typec_port
device generic 0 on end
end
chip drivers/intel/usb4/retimer
register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
use tcss_usb3_port1 as dfp[1].typec_port
device generic 0 on end
end
end
device ref tcss_dma1 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
use tcss_usb3_port2 as dfp[0].typec_port
device generic 0 on end
end
chip drivers/intel/usb4/retimer
register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
use tcss_usb3_port3 as dfp[1].typec_port
device generic 0 on end
end
end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
# FIXME - location need to be corrected once we have the final design
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C0""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C2""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(3, 1))"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C3""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
device ref usb2_port5 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A0""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(5, 1))"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A1""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(5, 2))"
device ref usb2_port7 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A2""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 3))"
device ref usb2_port8 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A3""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 4))"
device ref usb2_port9 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A4""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(5, 5))"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B01)"
device ref usb2_port10 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A0""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(5, 1))"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A1""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(5, 2))"
device ref usb3_port2 on end
end
end
end
end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
register "add_acpi_dma_property" = "true"
register "enable_cnvi_ddr_rfim" = "true"
device generic 0 on end
end
end
device ref i2c4 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E03_IRQ)"
device i2c 50 on end
end
end
device ref soc_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]
use conn1 as mux_conn[1]
use conn2 as mux_conn[2]
use conn3 as mux_conn[3]
device pnp 0c09.0 on end
end
end
device ref pmc hidden
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
#USB2_C0
use usb2_port2 as usb2_port
use tcss_usb3_port0 as usb3_port
device generic 0 alias conn0 on end
end
chip drivers/intel/pmc_mux/conn
#USB2_C1
use usb2_port3 as usb2_port
use tcss_usb3_port2 as usb3_port
device generic 1 alias conn1 on end
end
chip drivers/intel/pmc_mux/conn
#USB2_C2
use usb2_port1 as usb2_port
use tcss_usb3_port1 as usb3_port
device generic 2 alias conn2 on end
end
chip drivers/intel/pmc_mux/conn
#USB2_C3
use usb2_port5 as usb2_port
use tcss_usb3_port3 as usb3_port
device generic 3 alias conn3 on end
end
end
end
end
end
end
|
