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# SPDX-License-Identifier: GPL-2.0-or-later
chip soc/amd/phoenix
# eSPI Configuration
# TODO(b/276913952) bump clock back up to 33MHz once things seem to be working well.
register "common_config.espi_config" = "{
.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN,
.generic_io_range[0] = {
.base = 0x62,
.size = 1,
},
.generic_io_range[1] = {
.base = 0x66,
.size = 1,
},
.generic_io_range[2] = {
.base = 0x800, /* EC_HOST_CMD_REGION0 */
.size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */
},
.generic_io_range[3] = {
.base = 0x900, /* EC_LPC_ADDR_MEMMAP */
.size = 255, /* EC_MEMMAP_SIZE */
},
.generic_io_range[4] = {
.base = 0x200, /* EC_LPC_ADDR_HOST_DATA */
.size = 8, /* 0x200 - 0x207 */
},
.io_mode = ESPI_IO_MODE_QUAD,
.op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
.crc_check_enable = 1,
.alert_pin = ESPI_ALERT_PIN_OPEN_DRAIN,
.periph_ch_en = 1,
.vw_ch_en = 1,
.oob_ch_en = 0,
.flash_ch_en = 0,
.vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1),
}"
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
GPIO_I2C2_SCL | GPIO_I2C3_SCL"
# I2C Pad Control RX Select Configuration
register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" # Trackpad
register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" # Touchscreen
register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # GSC
register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # Speaker, Codec, P-SAR, USB
# I2C Config
#+-------------------+----------------------------+
#| Field | Value |
#+-------------------+----------------------------+
#| I2C0 | Trackpad |
#| I2C1 | Touchscreen |
#| I2C2 | GSC TPM |
#| I2C3 | Speaker, Codec, P-SAR, USB |
#+-------------------+----------------------------+
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
}"
register "i2c[1]" = "{
.speed = I2C_SPEED_FAST,
}"
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,
.early_init = true,
}"
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
}"
# general purpose PCIe clock output configuration
register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN
register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD
register "gpp_clk_config[2]" = "GPP_CLK_REQ" # WWAN
register "gpp_clk_config[3]" = "GPP_CLK_REQ" # SSD
register "gpp_clk_config[4]" = "GPP_CLK_OFF" # SOC_FP_BOOT0 GPIO
register "gpp_clk_config[5]" = "GPP_CLK_OFF" # WLAN_AUX_RST_L GPIO
register "gpp_clk_config[6]" = "GPP_CLK_OFF" # WWAN_AUX_RST_L GPIO
register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO(b/277214353): reenable when PSPP works
register "s0ix_enable" = "true"
register "usb_phy_custom" = "1"
register "usb_phy" = "{
.Usb2PhyPort[0] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[1] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[2] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[3] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[4] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[5] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[6] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[7] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb3PhyPort[0] = {
.tx_term_ctrl = 0x2,
.rx_term_ctrl = 0x2,
.tx_vboost_lvl_en = 0x0,
.tx_vboost_lvl = 0x5,
},
.Usb3PhyPort[1] = {
.tx_term_ctrl = 0x2,
.rx_term_ctrl = 0x2,
.tx_vboost_lvl_en = 0x0,
.tx_vboost_lvl = 0x5,
},
.Usb3PhyPort[2] = {
.tx_term_ctrl = 0x2,
.rx_term_ctrl = 0x2,
.tx_vboost_lvl_en = 0x0,
.tx_vboost_lvl = 0x5,
},
.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
.ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C,
.BatteryChargerEnable = 0,
.PhyP3CpmP4Support = 0,
}"
device domain 0 on
device ref gpp_bridge_2_1 on end # WWAN
device ref gpp_bridge_2_2 on # WLAN
chip drivers/wifi/generic
register "wake" = "GEVENT_8"
device pci 00.0 on end
end
end
device ref gpp_bridge_2_3 on end # SD
device ref gpp_bridge_2_4 on end # NVMe
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
device ref crypto on end # Crypto Coprocessor
device ref xhci_0 on # USB 3.1 (USB0)
chip drivers/usb/acpi
device ref xhci_0_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref usb3_port0 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref usb2_port0 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""User-Facing Camera""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""World-Facing Camera""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "has_power_resource" = "true"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_154)"
register "enable_delay_ms" = "500"
register "enable_off_delay_ms" = "200"
register "use_gpio_for_status" = "true"
device ref usb2_port4 on end
end
end
end
end
device ref acp on end # Audio Processor (ACP)
device ref mp2 on end # Sensor Fusion Hub (MP2)
end
device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
device ref usb4_xhci_0 on
chip drivers/usb/acpi
register "type" = "UPC_TYPE_HUB"
device ref usb4_xhci_0_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB4 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
device ref usb3_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB4 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
device ref usb2_port6 on end
end
end
end
end
device ref usb4_xhci_1 on
chip drivers/usb/acpi
register "type" = "UPC_TYPE_HUB"
device ref usb4_xhci_1_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB4 Type-C Port C1 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))"
device ref usb3_port7 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C1 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))"
device ref usb2_port7 on end
end
end
end
end
end
device ref iommu on end
device ref lpc_bridge on
chip ec/google/chromeec
device pnp 0c09.0 alias chrome_ec on end
end
end
end # domain
device ref uart_0 on end # UART0
device ref i2c_0 on end
device ref i2c_1 on end
device ref i2c_2 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "desc" = ""Ti50 TPM""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_84)"
device i2c 50 alias ti50 on end
end
end
device ref i2c_3 on end
end # chip soc/amd/phoenix
|
