1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <mainboard/google/link/onboard.h>
Scope (\_SB) {
Device (LID0)
{
Name(_HID, EisaId("PNP0C0D"))
Method(_LID, 0)
{
Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
Return (\LIDS)
}
// EC_LID_OUT is GPIO15
Name(_PRW, Package(){0x1f, 0x05})
}
Device (PWRB)
{
Name(_HID, EisaId("PNP0C0C"))
}
Device (TPAD)
{
Name (_ADR, 0x0)
Name (_UID, 1)
// Report as a Sleep Button device so Linux will
// automatically enable it as a wake source
Name(_HID, EisaId("PNP0C0E"))
// Trackpad Wake is GPIO12
Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 } )
Name(_CRS, ResourceTemplate()
{
// PIRQE -> GSI20
Interrupt (ResourceConsumer, Edge, ActiveLow)
{
BOARD_TRACKPAD_IRQ
}
// SMBUS Address 0x4b
VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR }
})
}
Device (TSCR)
{
Name (_ADR, 0x0)
Name (_UID, 2)
// Report as a Sleep Button device so Linux will
// automatically enable it as a wake source
Name(_HID, EisaId("PNP0C0E"))
// Touchscreen Wake is GPIO14
Name(_PRW, Package(){0x1e, 0x03})
Name(_CRS, ResourceTemplate()
{
// PIRQG -> GSI22
Interrupt (ResourceConsumer, Edge, ActiveLow) {22}
// SMBUS Address 0x4a
VendorShort (ADDR) {0x4a}
})
}
}
|
