summaryrefslogtreecommitdiff
path: root/src/mainboard/google/gru/devicetree.scarlet.cb
blob: f1129a4980ef5ee15fd7375b78ab9e3d695169fd (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
##
## This file is part of the coreboot project.
##
## Copyright 2017 Rockchip Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##

chip soc/rockchip/rk3399
	device cpu_cluster 0 on end
	register "vop_mode" = "VOP_MODE_MIPI"
	register "framebuffer_bits_per_pixel" = "32"
	register "panel_pixel_clock" = "56900"
	register "panel_refresh" = "60"
	register "panel_ha" = "768"
	register "panel_hbl" = "120"
	register "panel_hso" = "40"
	register "panel_hspw" = "40"
	register "panel_va" = "1024"
	register "panel_vbl" = "44"
	register "panel_vso" = "20"
	register "panel_vspw" = "4"
	register "panel_display_on_mdelay" = "120"
	register "panel_video_mode_mdelay" = "5"
end