1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
|
chip soc/intel/skylake
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # TPU
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM
register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # None
register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # HDMI
register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexSpi0] = PchSerialIoPci,
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
[PchSerialIoIndexUart0] = PchSerialIoSkipInit,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
device domain 0 on
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_LONG(OC_SKIP), // Type-C
[1] = USB2_PORT_MID(OC_SKIP), // HDMI
[2] = USB2_PORT_MID(OC2), // Type-A Rear
[3] = USB2_PORT_MID(OC2), // Type-A Rear
[4] = USB2_PORT_MID(OC3), // Type-A Rear
[5] = USB2_PORT_MID(OC_SKIP), // HDMI Audio
[6] = USB2_PORT_MID(OC_SKIP), // Bluetooth
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C
[1] = USB3_PORT_DEFAULT(OC_SKIP), // HDMI
[2] = USB3_PORT_DEFAULT(OC2), // Type-A Rear
[3] = USB3_PORT_DEFAULT(OC2), // Type-A Rear
[4] = USB3_PORT_DEFAULT(OC3), // Type-A Rear
}"
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""USB2 HDMI In""
register "type" = "UPC_TYPE_INTERNAL"
device usb 2.1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Rear Left""
register "type" = "UPC_TYPE_A"
device usb 2.2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Rear Middle""
register "type" = "UPC_TYPE_A"
device usb 2.3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Rear Right""
register "type" = "UPC_TYPE_A"
device usb 2.4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 HDMI Audio In""
register "type" = "UPC_TYPE_INTERNAL"
device usb 2.5 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 HDMI Video In""
register "type" = "UPC_TYPE_INTERNAL"
device usb 3.1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Rear Left""
register "type" = "UPC_TYPE_USB3_A"
device usb 3.2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Rear Middle""
register "type" = "UPC_TYPE_USB3_A"
device usb 3.3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Rear Right""
register "type" = "UPC_TYPE_USB3_A"
device usb 3.4 on end
end
device usb 3.5 off end
end
end
end
device ref i2c3 on
chip drivers/i2c/generic
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "desc" = ""Chrontel 7322""
register "uid" = "1"
register "compat_string" = ""chrontel,ch7322""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A18)"
device i2c 75 on end
end
chip drivers/i2c/generic
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "desc" = ""Chrontel 7322""
register "uid" = "2"
register "compat_string" = ""chrontel,ch7322""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A20)"
device i2c 76 on end
end
end
device ref i2c5 on
chip drivers/i2c/generic
register "hid" = ""10EC5663""
register "name" = ""RT53""
register "desc" = ""Realtek RT5663""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
device i2c 13 on end
end
end
device ref pcie_rp7 on
# x1 TPU1
register "PcieRpEnable[6]" = "1"
register "PcieRpClkReqSupport[6]" = "1"
register "PcieRpClkReqNumber[6]" = "4"
register "PcieRpAdvancedErrorReporting[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpClkSrcNumber[6]" = "4"
end
device ref pcie_rp8 on
# x1 TPU0
register "PcieRpEnable[7]" = "1"
register "PcieRpClkReqSupport[7]" = "1"
register "PcieRpClkReqNumber[7]" = "2"
register "PcieRpAdvancedErrorReporting[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpClkSrcNumber[7]" = "2"
end
device ref pcie_rp9 on
# x4 i350 LAN
register "PcieRpEnable[8]" = "1"
register "PcieRpClkReqSupport[8]" = "0"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpClkSrcNumber[8]" = "2"
end
device ref pcie_rp10 off
register "PcieRpEnable[9]" = "0"
end
device ref pcie_rp11 off
register "PcieRpEnable[10]" = "0"
end
device ref pcie_rp12 off
register "PcieRpEnable[11]" = "0"
end
end
end
|
