path: root/src/mainboard/google/dedede/variants/baseboard/devicetree.cb

fw_config
	field DB_PORTS 0 3
		option DB_PORTS_NONE 0
		option DB_PORTS_2C_2A 1
		option DB_PORTS_1C_LTE 2
		option DB_PORTS_1A_HDMI 3
		option DB_PORTS_1C_1A 4
		option DB_PORTS_LTE_HDMI 5
		option DB_PORTS_1C_1A_LTE 6
		option DB_PORTS_1C 7
		option DB_PORTS_1A_HDMI_LTE 8
	end
	field STYLUS 4
		option STYLUS_ABSENT 0
		option STYLUS_PRESENT 1
	end
        field TABLETMODE 10
                option TABLETMODE_DISABLED 0
                option TABLETMODE_ENABLED 1
        end
	field AUDIO_AMP 14 16
		option UNPROVISIONED 0
		option MAX98360 1
		option RT1015_I2C 2
		option RT1015P_AUTO 3
		option ALC5650 4
	end
	field LTE 11
		option LTE_ABSENT 0
		option LTE_PRESENT 1
	end
	field EXT_VR 18
		option EXT_VR_PRESENT 0
		option EXT_VR_ABSENT 1
	end
end

chip soc/intel/jasperlake
	device cpu_cluster 0 on end

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route, i.e., if this route changes then the affected GPE
	# offset bits also need to be changed.
	# DW0 is used by:
	#   - GPP_B3 - TRACKPAD_INT_ODL
	#   - GPP_B4 - H1_AP_INT_ODL
	# DW1 is used by:
	#   - GPP_C12 - AP_PEN_DET_ODL
	# DW2 is used by:
	#   - GPP_D0 - WWAN_HOST_WAKE
	#   - GPP_D3 - WLAN_PCIE_WAKE_ODL
	# EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3.
	register "pmc_gpe0_dw0" = "PMC_GPP_B"
	register "pmc_gpe0_dw1" = "PMC_GPP_C"
	register "pmc_gpe0_dw2" = "PMC_GPP_D"

	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
	register "gen1_dec" = "0x00fc0801"
	register "gen2_dec" = "0x000c0201"
	# EC memory map range is 0x900-0x9ff
	register "gen3_dec" = "0x00fc0901"

	# USB Port Configuration
	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-C Port C0
	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-C Port C1
	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A1
	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# Discrete Bluetooth
	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Integrated Bluetooth

	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type-C Port C0
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type-C Port C1
	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/1 Type-A Port A0
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/1 Type-A Port A1

	register "SerialIoI2cMode" = "{
		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
	}"

	register "SerialIoGSpiMode" = "{
		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
	}"

	register "SerialIoGSpiCsMode" = "{
		[PchSerialIoIndexGSPI0] = 1,
		[PchSerialIoIndexGSPI1] = 0,
		[PchSerialIoIndexGSPI2] = 0,
	}"

	register "SerialIoGSpiCsState" = "{
		[PchSerialIoIndexGSPI0] = 0,
		[PchSerialIoIndexGSPI1] = 0,
		[PchSerialIoIndexGSPI2] = 0,
	}"

	register "SerialIoUartMode" = "{
		[PchSerialIoIndexUART0] = PchSerialIoDisabled,
		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
	}"

	# PCIE Root Port Configuration
	register "PcieRpEnable[0]" = "0"
	register "PcieRpEnable[1]" = "0"
	register "PcieRpEnable[2]" = "0"
	register "PcieRpEnable[3]" = "0"
	register "PcieRpEnable[4]" = "0"
	register "PcieRpEnable[5]" = "0"
	register "PcieRpEnable[6]" = "0"
	# PCIe Root Port 8 (index 7) hosts M.2 E-key WLAN.
	register "PcieRpEnable[7]" = "1"

	register "PcieClkSrcUsage[0]" = "0xff"
	register "PcieClkSrcUsage[1]" = "0xff"
	register "PcieClkSrcUsage[2]" = "0xff"
	# PCIe Clock Source 4 (index 3) is used by WLAN on PCIe Root Port 8 (index 7)
	register "PcieClkSrcUsage[3]" = "7"
	register "PcieClkSrcUsage[4]" = "0xff"
	register "PcieClkSrcUsage[5]" = "0xff"

	# PCIE Clock Request to Clock Source Mapping
	register "PcieClkSrcClkReq[0]" = "0"
	register "PcieClkSrcClkReq[1]" = "1"
	register "PcieClkSrcClkReq[2]" = "2"
	register "PcieClkSrcClkReq[3]" = "3"
	register "PcieClkSrcClkReq[4]" = "4"
	register "PcieClkSrcClkReq[5]" = "5"

	# Audio related configurations
	register "PchHdaDspEnable" = "1"
	register "PchHdaAudioLinkHdaEnable" = "1"
	register "PchHdaAudioLinkSspEnable[0]" = "1"
	register "PchHdaAudioLinkSspEnable[1]" = "1"
	register "PchHdaAudioLinkDmicEnable[0]" = "1"
	register "PchHdaAudioLinkDmicEnable[1]" = "1"

	# Enable EMMC HS400 mode
	register "ScsEmmcHs400Enabled" = "1"

	# GPIO for SD card detect
	register "sdcard_cd_gpio" = "VGPIO_39"
	# SD card power enable polarity
	register "SdCardPowerEnableActiveHigh" = "1"

	# Enable S0ix support
	register "s0ix_enable" = "1"

	# Display related UPDs
	# Select eDP for port A
	register "DdiPortAConfig" = "1"

	# Enable HPD for DDI ports B/C
	register "DdiPortBHpd" = "1"
	register "DdiPortCHpd" = "1"
	# Enable DDC for DDI ports B/C
	register "DdiPortBDdc" = "1"
	register "DdiPortCDdc" = "1"

	# Enable DPTF
	register "dptf_enable" = "1"

	# Power limit config
	register "power_limits_config[JSL_N4500_6W_CORE]" = "{
		.tdp_pl1_override = 6,
		.tdp_pl2_override = 20,
	}"

	register "power_limits_config[JSL_N6000_6W_CORE]" = "{
		.tdp_pl1_override = 6,
		.tdp_pl2_override = 20,
	}"

	register "power_limits_config[JSL_N5100_6W_CORE]" = "{
		.tdp_pl1_override = 6,
		.tdp_pl2_override = 20,
	}"

	register "power_limits_config[JSL_N4505_10W_CORE]" = "{
		.tdp_pl1_override = 10,
		.tdp_pl2_override = 25,
	}"

	register "power_limits_config[JSL_N5105_10W_CORE]" = "{
		.tdp_pl1_override = 10,
		.tdp_pl2_override = 25,
	}"

	register "power_limits_config[JSL_N6005_10W_CORE]" = "{
		.tdp_pl1_override = 10,
		.tdp_pl2_override = 25,
	}"

	register "tcc_offset" = "10"     # TCC of 90C

	# VR config settings
	# Imon Slope correction specified in 1/100 increment values. Range is 0-200.
	# Eg: 125 = 1.25
	register "ImonSlope" = "100"

	# Imon offset correction. Value is a 2's complement signed integer.
	# Units 1/1000, Range 0-63999.
	# For an offset = 12.580, use 12580
	register "ImonOffset" = "0"

	# Skip the CPU replacement check
	register "SkipCpuReplacementCheck" = "1"

	# Sagv Configuration
	register "SaGv" = "SaGv_Enabled"

	# Set the minimum assertion width
	register "PchPmSlpS3MinAssert"  = "3"  # 50ms
	register "PchPmSlpS4MinAssert"  = "1"  # 1s
	register "PchPmSlpSusMinAssert" = "3"  # 1s
	register "PchPmSlpAMinAssert"   = "3"  # 98ms

	# NOTE: Duration programmed in the below register should never be smaller than the
	# stretch duration programmed in the following registers -
	#       - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
	#       - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
	#       - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
	#       - PM_CFG.SLP_LAN_MIN_ASST_WDTH
	register "PchPmPwrCycDur" = "1"       # 1s

	# Set xHCI LFPS period sampling off time, the default is 9ms.
	register "xhci_lfps_sampling_offtime_ms" = "9"

	device domain 0 on
		device pci 00.0 on end # Host Bridge
		device pci 02.0 on
			register "gfx" = "GMA_DEFAULT_PANEL(0)"
		end # Integrated Graphics Device
		device pci 04.0 on
			# Default DPTF Policy for all Dedede boards if not overridden
			chip drivers/intel/dptf
				## Passive Policy
				register "policies.passive" = "{
					[0] = DPTF_PASSIVE(CPU, CPU,           90, 10000),
					[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000),
					[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000),
					[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 15000)
				}"

				## Critical Policy
				register "policies.critical" = "{
					[0] = DPTF_CRITICAL(CPU,           105, SHUTDOWN),
					[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
					[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN),
					[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN)
				}"

				## Power Limits Control
				register "controls.power_limits" = "{
					.pl1 = {
						.min_power = 3000,
						.max_power = 6000,
						.time_window_min = 1 * MSECS_PER_SEC,
						.time_window_max = 1 * MSECS_PER_SEC,
						.granularity = 200,
					},
					.pl2 = {
						.min_power = 20000,
						.max_power = 20000,
						.time_window_min = 1 * MSECS_PER_SEC,
						.time_window_max = 1 * MSECS_PER_SEC,
						.granularity = 1000,
					}
				}"

				register "options.tsr[0].desc" = ""Memory""
				register "options.tsr[1].desc" = ""Ambient""
				register "options.tsr[2].desc" = ""Charger""

				## Charger Performance Control (Control, mA)
				register "controls.charger_perf" = "{
					[0] = { 255, 3000 },
					[1] = {  24, 1500 },
					[2] = {  16, 1000 },
					[3] = {   8,  500 }
				}"

				device generic 0 on end
			end
		end # SA Thermal device
		device pci 05.0 off end # IPU
		device pci 09.0 off end # Intel Trace Hub
		device pci 12.6 off end # GSPI 2
		device pci 14.0 on
			chip drivers/usb/acpi
				register "desc" = ""Root Hub""
				register "type" = "UPC_TYPE_HUB"
				device usb 0.0 on
					chip drivers/usb/acpi
						register "desc" = ""Left Type-C Port""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "group" = "ACPI_PLD_GROUP(1, 1)"
						device usb 2.0 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Right Type-C Port""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "group" = "ACPI_PLD_GROUP(2, 1)"
						device usb 2.1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Left Type-A Port""
						register "type" = "UPC_TYPE_A"
						register "group" = "ACPI_PLD_GROUP(1, 2)"
						device usb 2.2 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Right Type-A Port""
						register "type" = "UPC_TYPE_A"
						register "group" = "ACPI_PLD_GROUP(2, 2)"
						device usb 2.3 on end
					end
					chip drivers/usb/acpi
						device usb 2.4 off end
					end
					chip drivers/usb/acpi
						device usb 2.5 off end
					end
					chip drivers/usb/acpi
						device usb 2.6 off end
					end
					chip drivers/usb/acpi
						register "desc" = ""Bluetooth""
						register "type" = "UPC_TYPE_INTERNAL"
						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)"
						device usb 2.7 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Left Type-C Port""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "group" = "ACPI_PLD_GROUP(1, 1)"
						device usb 3.0 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Right Type-C Port""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "group" = "ACPI_PLD_GROUP(2, 1)"
						device usb 3.1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Left Type-A Port""
						register "type" = "UPC_TYPE_USB3_A"
						register "group" = "ACPI_PLD_GROUP(1, 2)"
						device usb 3.2 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Right Type-A Port""
						register "type" = "UPC_TYPE_USB3_A"
						register "group" = "ACPI_PLD_GROUP(2, 2)"
						device usb 3.3 on end
					end
				end
			end
		end # USB xHCI
		device pci 14.1 off end # USB xDCI (OTG)
		device pci 14.2 off end # PMC SRAM
		device pci 14.3 on
			chip drivers/wifi/generic
				register "wake" = "GPE0_PME_B0"
				device generic 0 on end
			end
		end # CNVi wifi
		device pci 14.5 on  end # SDCard
		device pci 15.0 on  end # I2C 0
		device pci 15.1 on  end # I2C 1
		device pci 15.2 on  end # I2C 2
		device pci 15.3 on  end # I2C 3
		device pci 16.0 on  end # HECI 1
		device pci 16.1 off end # HECI 2
		device pci 16.4 off end # HECI 3
		device pci 16.5 off end # HECI 4
		device pci 17.0 off end # SATA
		device pci 19.0 on  end # I2C 4
		device pci 19.1 off end # I2C 5
		device pci 19.2 on  end # UART 2
		device pci 1a.0 on  end # eMMC
		device pci 1c.0 off end # PCI Express Root Port 1
		device pci 1c.1 off end # PCI Express Root Port 2
		device pci 1c.2 off end # PCI Express Root Port 3
		device pci 1c.3 off end # PCI Express Root Port 4
		device pci 1c.4 off end # PCI Express Root Port 5
		device pci 1c.5 off end # PCI Express Root Port 6
		device pci 1c.6 off end # PCI Express Root Port 7
		# External PCIe port 4 is mapped to PCIe Root port 8
		device pci 1c.7 on  end # PCI Express Root Port 8 - WLAN
		device pci 1e.0 off end # UART 0
		device pci 1e.1 off end # UART 1
		device pci 1e.2 on
			chip drivers/spi/acpi
				register "hid" = "ACPI_DT_NAMESPACE_HID"
				register "compat_string" = ""google,cr50""
				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)"
				device spi 0 on end
			end
		end # GSPI 0
		device pci 1e.3 off end # GSPI 1
		device pci 1f.0 on
			chip ec/google/chromeec
				device pnp 0c09.0 on end
			end
		end # eSPI Interface
		device pci 1f.1 on  end # P2SB
		device pci 1f.2 hidden end # Power Management Controller
		device pci 1f.3 on
			chip drivers/sof
				register "spkr_tplg" = "rt1015"
				register "jack_tplg" = "rt5682"
				register "mic_tplg" = "_2ch_pdm0"
				device generic 0 on
					probe AUDIO_AMP RT1015_I2C
					probe AUDIO_AMP RT1015P_AUTO
					probe AUDIO_AMP UNPROVISIONED
				end
			end
			chip drivers/sof
				register "spkr_tplg" = "max98360a"
				register "jack_tplg" = "rt5682"
				register "mic_tplg" = "_2ch_pdm0"
				device generic 0 on
					probe AUDIO_AMP MAX98360
				end
			end
		end # Intel HDA/cAVS
		device pci 1f.4 off end # SMBus
		device pci 1f.5 on  end # PCH SPI
		device pci 1f.7 off end # Intel Trace Hub
	end
end