blob: 65e662c5dd6c5d7850f175b55a8f0f8d384062af (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
|
chip soc/intel/braswell
############################################################
# Set the parameters for MemoryInit
############################################################
register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB
register "PcdMrcInitMmioSize" = "0x0800"
register "PcdMrcInitSpdAddr1" = "0xa0"
register "PcdMrcInitSpdAddr2" = "0xa2"
register "PcdIgdDvmt50PreAlloc" = "1"
register "PcdApertureSize" = "2"
register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "1"
register "PcdCaMirrorEn" = "1"
############################################################
# Set the parameters for SiliconInit
############################################################
register "PcdSdcardMode" = "PCH_ACPI_MODE"
register "PcdEnableHsuart0" = "0"
register "PcdEnableHsuart1" = "1"
register "PcdEnableAzalia" = "1"
register "PcdEnableXhci" = "1"
register "PcdEnableLpe" = "1"
register "PcdEnableDma0" = "1"
register "PcdEnableDma1" = "1"
register "PcdEnableI2C0" = "1"
register "PcdEnableI2C1" = "1"
register "PcdEnableI2C2" = "0"
register "PcdEnableI2C3" = "0"
register "PcdEnableI2C4" = "1"
register "PcdEnableI2C5" = "1"
register "PcdEnableI2C6" = "0"
register "PunitPwrConfigDisable" = "0" # Enable SVID
register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
register "PcdEmmcMode" = "PCH_ACPI_MODE"
register "PcdUsb3ClkSsc" = "1"
register "PcdDispClkSsc" = "1"
register "PcdSataClkSsc" = "1"
register "PcdEnableSata" = "0" # Disable SATA
register "Usb2Port0PerPortPeTxiSet" = "7"
register "Usb2Port0PerPortTxiSet" = "5"
register "Usb2Port0IUsbTxEmphasisEn" = "2"
register "Usb2Port0PerPortTxPeHalf" = "1"
register "Usb2Port1PerPortPeTxiSet" = "7"
register "Usb2Port1PerPortTxiSet" = "3"
register "Usb2Port1IUsbTxEmphasisEn" = "2"
register "Usb2Port1PerPortTxPeHalf" = "1"
register "Usb2Port2PerPortPeTxiSet" = "7"
register "Usb2Port2PerPortTxiSet" = "3"
register "Usb2Port2IUsbTxEmphasisEn" = "2"
register "Usb2Port2PerPortTxPeHalf" = "1"
register "Usb2Port3PerPortPeTxiSet" = "7"
register "Usb2Port3PerPortTxiSet" = "3"
register "Usb2Port3IUsbTxEmphasisEn" = "2"
register "Usb2Port3PerPortTxPeHalf" = "1"
register "Usb2Port4PerPortPeTxiSet" = "7"
register "Usb2Port4PerPortTxiSet" = "3"
register "Usb2Port4IUsbTxEmphasisEn" = "2"
register "Usb2Port4PerPortTxPeHalf" = "1"
register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
register "PcdSataInterfaceSpeed" = "3"
register "PcdPchSsicEnable" = "1"
register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM
register "PMIC_I2CBus" = "1"
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"
register "PcdSdDetectChk" = "0" # Disable SD card detect
register "I2C0Frequency" = "1"
register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz
register "I2C2Frequency" = "1"
register "I2C3Frequency" = "1"
register "I2C4Frequency" = "1"
register "I2C5Frequency" = "1"
register "I2C6Frequency" = "1"
# Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength)
register "D0Usb2Port0PerPortRXISet" = "2"
register "D0Usb2Port1PerPortRXISet" = "2"
register "D0Usb2Port2PerPortRXISet" = "2"
register "D0Usb2Port3PerPortRXISet" = "2"
register "D0Usb2Port4PerPortRXISet" = "2"
# LPE audio codec settings
register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
# Enable devices in ACPI mode
register "lpss_acpi_mode" = "1"
register "emmc_acpi_mode" = "1"
register "sd_acpi_mode" = "1"
register "lpe_acpi_mode" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
# Allow PCIe devices to wake system from suspend
register "pcie_wake_enable" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
# EDS Table 24-4, Figure 24-5
device pci 00.0 on end # 8086 2280 - SoC transaction router
device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
device pci 03.0 off end # 8086 22b8 - Camera and Image Processor
device pci 0b.0 on end # 8086 22dc - ?
device pci 10.0 on end # 8086 2294 - MMC Port
device pci 11.0 off end # 8086 0F15 - SDIO Port
device pci 12.0 on end # 8086 0F16 - SD Port
device pci 13.0 off end # 8086 22a3 - Sata controller
device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time
device pci 15.0 on end # 8086 22a8 - LP Engine Audio
device pci 16.0 off end # 8086 22b7 - USB device
device pci 18.0 on end # 8086 22c0 - SIO - DMA
device pci 18.1 on end # 8086 22c1 - I2C Port 1
device pci 18.2 on end # 8086 22c2 - I2C Port 2
device pci 18.3 off end # 8086 22c3 - I2C Port 3
device pci 18.4 off end # 8086 22c4 - I2C Port 4
device pci 18.5 on end # 8086 22c5 - I2C Port 5
device pci 18.6 on end # 8086 22c6 - I2C Port 6
device pci 18.7 off end # 8086 22c7 - I2C Port 7
device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine
device pci 1b.0 on end # 8086 0F04 - HD Audio
device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1
device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2
device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3
device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4
device pci 1e.0 on end # 8086 2286 - SIO - DMA
device pci 1e.1 off end # 8086 0F08 - PWM 1
device pci 1e.2 off end # 8086 0F09 - PWM 2
device pci 1e.3 off end # 8086 228a - HSUART 1
device pci 1e.4 off end # 8086 228c - HSUART 2
device pci 1e.5 on end # 8086 228e - SPI 1
device pci 1e.6 off end # 8086 2290 - SPI 2
device pci 1e.7 off end # 8086 22ac - SPI 3
device pci 1f.0 on # 8086 229c - LPC bridge
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end # LPC Bridge
device pci 1f.3 off end # 8086 0F12 - SMBus 0
end
end
|
