overridetree.cb « celes « variants « cyan « google « mainboard « src - coreboot.git - my copy of coreboot

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path: root/src/mainboard/google/cyan/variants/celes/overridetree.cb

blob: 1eabd8e3153c0e2fc6aca647cb463c7f8edaf6c7 (plain)

chip soc/intel/braswell

	register "PcdPchSsicEnable" = "0"
	register "PcdPchUsbHsicPort" = "0"

	device domain 0 on end

end