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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/romstage.h>
#include <baseboard/variants.h>
#include "spd/spd_util.h"
/* All FSP specific code goes in this block */
void mainboard_romstage_entry(struct romstage_params *rp)
{
/* Call back into chipset code with platform values updated. */
romstage_common(rp);
}
void mainboard_memory_init_params(struct romstage_params *params,
MEMORY_INIT_UPD *memory_params)
{
spd_memory_init_params(memory_params);
/* Variant-specific memory params */
variant_memory_init_params(memory_params);
}
__weak
void variant_memory_init_params(MEMORY_INIT_UPD *memory_params)
{
}
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