summaryrefslogtreecommitdiff
path: root/src/mainboard/google/brya/variants/riven/overridetree.cb
blob: 301d72a966938ea032de2504ee28b59e3626c19f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
fw_config
	field DB_USB 0 1
		option DB_NONE			0
		option DB_1C_1A			1
		option DB_1C_LTE		2
	end
	field STYLUS 2
		option STYLUS_ABSENT		0
		option STYLUS_PRESENT		1
	end
	field WIFI_TYPE 7
		option WIFI_CNVI		0
		option WIFI_PCIE		1
	end
	field WFC 9 10
		option WFC_ABSENT		0
		option WFC_MIPI_OVTI5675	1
		option WFC_MIPI_OVTI8856	2
	end
end

chip soc/intel/alderlake
	register "sagv" = "SaGv_Enabled"

	# EMMC Tx CMD Delay
	# Refer to EDS-Vol2-42.3.7.
	# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
	# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
	register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"

	# EMMC TX DATA Delay 1
	# Refer to EDS-Vol2-42.3.8.
	# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
	# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"

	# EMMC TX DATA Delay 2
	# Refer to EDS-Vol2-42.3.9.
	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
	# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"

	# EMMC RX CMD/DATA Delay 1
	# Refer to EDS-Vol2-42.3.10.
	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F3C"

	# EMMC RX CMD/DATA Delay 2
	# Refer to EDS-Vol2-42.3.12.
	# [17:16] stands for Rx Clock before Output Buffer,
	#         00: Rx clock after output buffer,
	#         01: Rx clock before output buffer,
	#         10: Automatic selection based on working mode.
	#         11: Reserved
	# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
	# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023"

	# EMMC Rx Strobe Delay
	# Refer to EDS-Vol2-42.3.11.
	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515"

	# SOC Aux orientation override:
	# This is a bitfield that corresponds to up to 4 TCSS ports.
	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
	# TcssAuxOri = 0101b
	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
	# motherboard to USBC connector
	register "tcss_aux_ori" = "5"

	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
	register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"

	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for PCIe WLAN
	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN

	# Configure external V1P05/Vnn/VnnSx Rails
	register "ext_fivr_settings" = "{
		.configure_ext_fivr = 1,
		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
		.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
		.v1p05_voltage_mv = 1050,
		.vnn_voltage_mv = 780,
		.vnn_sx_voltage_mv = 1050,
		.v1p05_icc_max_ma = 500,
		.vnn_icc_max_ma = 500,
	}"

	# Enable the Cnvi BT Audio Offload
	register "cnvi_bt_audio_offload" = "1"

	# Intel Common SoC Config
	#+-------------------+---------------------------+
	#| Field             |  Value                    |
	#+-------------------+---------------------------+
	#| I2C0              | TPM. Early init is        |
	#|                   | required to set up a BAR  |
	#|                   | for TPM communication     |
	#| I2C1              | Touchscreen               |
	#| I2C2              | Sub-board(PSensor)/WCAM   |
	#| I2C3              | Audio                     |
	#| I2C5              | Trackpad                  |
	#+-------------------+---------------------------+
	register "common_soc_config" = "{
		.i2c[0] = {
			.early_init = 1,
			.speed = I2C_SPEED_FAST_PLUS,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST_PLUS,
				.scl_lcnt = 55,
				.scl_hcnt = 30,
				.sda_hold = 7,
			}
		},
		.i2c[1] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 158,
				.scl_hcnt = 79,
				.sda_hold = 30,
			}
		},
		.i2c[2] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 158,
				.scl_hcnt = 79,
				.sda_hold = 7,
			}
		},
		.i2c[3] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 158,
				.scl_hcnt = 79,
				.sda_hold = 7,
			}
		},
		.i2c[5] = {
			.speed = I2C_SPEED_FAST,
			.speed_config[0] = {
				.speed = I2C_SPEED_FAST,
				.scl_lcnt = 158,
				.scl_hcnt = 79,
				.sda_hold = 40,
			}
		},
	}"

	device domain 0 on
		device ref dtt on
			chip drivers/intel/dptf
				## sensor information
				register "options.tsr[0].desc" = ""Memory""
				register "options.tsr[1].desc" = ""Charger""
				register "options.tsr[2].desc" = ""Ambient""

				# TODO: below values are initial reference values only
				## Passive Policy
				register "policies.passive" = "{
					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
					[3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2, 75, 5000),
				}"

				## Critical Policy
				register "policies.critical" = "{
					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
				}"

				register "controls.power_limits" = "{
					.pl1 = {
							.min_power = 5500,
							.max_power = 6000,
							.time_window_min = 28 * MSECS_PER_SEC,
							.time_window_max = 28 * MSECS_PER_SEC,
							.granularity = 200
						},
					.pl2 = {
							.min_power = 25000,
							.max_power = 25000,
							.time_window_min = 1,
							.time_window_max = 1,
							.granularity = 1000
						}
				}"

				## Charger Performance Control (Control, mA)
				register "controls.charger_perf" = "{
					[0] = { 255, 1700 },
					[1] = {  24, 1500 },
					[2] = {  16, 1000 },
					[3] = {   8,  500 }
				}"

				device generic 0 on end
			end
		end
		device ref ipu on
			chip drivers/intel/mipi_camera
				register "acpi_uid" = "0x50000"
				register "acpi_name" = ""IPU0""
				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"

				register "cio2_num_ports" = "1"
				register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used
				register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0""
				register "cio2_prt[0]" = "1"
				device generic 0 on end
			end
			probe WFC WFC_MIPI_OVTI5675
			probe WFC WFC_MIPI_OVTI8856
		end
		device ref cnvi_wifi on
			chip drivers/wifi/generic
				register "enable_cnvi_ddr_rfim" = "true"
				device generic 0 on
					probe WIFI_TYPE WIFI_CNVI
				end
			end
		end
		device ref i2c1 on
			chip drivers/i2c/hid
				register "generic.hid" = ""ELAN9004""
				register "generic.desc" = ""ELAN Touchscreen""
				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
				register "generic.detect" = "1"
				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
				register "generic.reset_delay_ms" = "20"
				register "generic.reset_off_delay_ms" = "2"
				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
				register "generic.stop_delay_ms" = "280"
				register "generic.stop_off_delay_ms" = "2"
				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
				register "generic.enable_delay_ms" = "1"
				register "generic.has_power_resource" = "1"
				register "hid_desc_reg_offset" = "0x01"
				device i2c 10 on end
			end
			chip drivers/generic/gpio_keys
				register "name" = ""PENH""
				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"
				register "key.wake_gpe" = "GPE0_DW2_15"
				register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
				register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
				register "key.dev_name" = ""EJCT""
				register "key.linux_code" = "SW_PEN_INSERTED"
				register "key.linux_input_type" = "EV_SW"
				register "key.label" = ""pen_eject""
				device generic 0 on
					probe STYLUS STYLUS_PRESENT
				end
			end
		end
		device ref i2c2 on
			chip drivers/intel/mipi_camera
				register "acpi_hid" = ""OVTI5675""
				register "acpi_uid" = "0"
				register "acpi_name" = ""CAM0""
				register "chip_name" = ""Ov 5675 Camera""
				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"

				register "ssdb.lanes_used" = "2"
				register "ssdb.link_used" = "1"
				register "ssdb.vcm_type" = "0x0C"
				register "vcm_name" = ""VCM0""
				register "num_freq_entries" = "1"
				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
				register "remote_name" = ""IPU0""

				register "has_power_resource" = "1"
				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"

				#Controls
				register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"

				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15"  # EN_PP2800_WCAM_X
				register "gpio_panel.gpio[1].gpio_num" = "GPP_D16"  # EN_PP1800_PP1200_WCAM_X
				register "gpio_panel.gpio[2].gpio_num" = "GPP_D3"   # WCAM_RST_L

				#_ON
				register "on_seq.ops_cnt" = "5"
				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"

				#_OFF
				register "off_seq.ops_cnt" = "4"
				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"

				device i2c 36 on
					probe WFC WFC_MIPI_OVTI5675
				end
			end
			chip drivers/intel/mipi_camera
				register "acpi_hid" = ""OVTI8856""
				register "acpi_uid" = "0"
				register "acpi_name" = ""CAM0""
				register "chip_name" = ""Ov 8856 Camera""
				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
				register "has_power_resource" = "1"
				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"

				register "ssdb.lanes_used" = "2"
				register "ssdb.link_used" = "1"
				register "ssdb.vcm_type" = "0x0C"
				register "vcm_name" = ""VCM0""
				register "num_freq_entries" = "2"
				register "link_freq[0]" = "720000000"
				register "link_freq[1]" = "360000000"
				register "remote_name" = ""IPU0""

				#Controls
				register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
				register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"

				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15"  # EN_PP2800_WCAM_X
				register "gpio_panel.gpio[1].gpio_num" = "GPP_D16"  # EN_PP1800_PP1200_WCAM_X
				register "gpio_panel.gpio[2].gpio_num" = "GPP_D3"   # WCAM_RST_L

				#_ON
				register "on_seq.ops_cnt" = "5"
				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
				register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"

				#_OFF
				register "off_seq.ops_cnt" = "4"
				register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
				register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
				register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"

				device i2c 10 on
					probe WFC WFC_MIPI_OVTI8856
				end
			end
			chip drivers/intel/mipi_camera
				register "acpi_uid" = "3"
				register "acpi_name" = ""VCM0""
				register "chip_name" = ""DW AF DAC""
				register "device_type" = "INTEL_ACPI_CAMERA_VCM"

				register "vcm_compat" = ""dongwoon,dw9714""
				register "has_power_resource" = "1"
				register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"

				#Controls
				register "gpio_panel.gpio[0].gpio_num" = "GPP_D15"  # EN_PP2800_WCAM_X

				#_ON
				register "on_seq.ops_cnt" = "1"
				register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"

				#_OFF
				register "off_seq.ops_cnt" = "1"
				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"

				device i2c 0C on
					probe WFC WFC_MIPI_OVTI5675
					probe WFC WFC_MIPI_OVTI8856
				end
			end
			chip drivers/intel/mipi_camera
				register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
				register "acpi_uid" = "1"
				register "acpi_name" = ""NVM0""
				register "chip_name" = ""GT24C08""
				register "device_type" = "INTEL_ACPI_CAMERA_NVM"

				register "nvm_size" = "0x2000"
				register "nvm_pagesize" = "1"
				register "nvm_readonly" = "1"
				register "nvm_width" = "0x10"
				register "nvm_compat" = ""atmel,24c08""

				device i2c 50 on
					probe WFC WFC_MIPI_OVTI5675
					probe WFC WFC_MIPI_OVTI8856
				end
			end
		end
		device ref i2c3 on
                        chip drivers/i2c/generic
				register "hid" = ""RTL5682""
				register "name" = ""RT58""
				register "desc" = ""Headset Codec""
				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
				# Set the jd_src to RT5668_JD1 for jack detection
				register "property_count" = "1"
				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
				register "property_list[0].name" = ""realtek,jd-src""
				register "property_list[0].integer" = "1"
				device i2c 1a on end
			end
			chip drivers/generic/alc1015
				register "hid" = ""RTL1019""
				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
				device generic 0 on end
			end
		end
		device ref i2c5 on
			chip drivers/i2c/generic
				register "hid" = ""ELAN0000""
				register "desc" = ""ELAN Touchpad""
				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
				register "wake" = "GPE0_DW2_14"
				register "detect" = "1"
				device i2c 15 on end
			end
			chip drivers/i2c/hid
				register "generic.hid" = ""SYNA0000""
				register "generic.cid" = ""ACPI0C50""
				register "generic.desc" = ""Synaptics Touchpad""
				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
				register "generic.wake" = "GPE0_DW2_14"
				register "generic.detect" = "1"
				register "hid_desc_reg_offset" = "0x20"
				device i2c 0x2c on end
			end
		end
		device ref hda on
			chip drivers/sof
				register "spkr_tplg" = "rt1019"
				register "jack_tplg" = "rt5682"
				register "mic_tplg" = "_2ch_pdm0"
				device generic 0 on end
			end
		end
		device ref pcie_rp4 on
			probe WIFI_TYPE WIFI_PCIE
			# Enable wlan PCIe 4 using clk 2
			register "pch_pcie_rp[PCH_RP(4)]" = "{
				.clk_src = 2,
				.clk_req = 2,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
			chip drivers/wifi/generic
				register "wake" = "GPE0_DW1_03"
				register "add_acpi_dma_property" = "true"
				device pci 00.0 on
					probe WIFI_TYPE WIFI_PCIE
				end
			end
			chip soc/intel/common/block/pcie/rtd3
				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
				register "srcclk_pin" = "2"
				device generic 0 on
					probe WIFI_TYPE WIFI_PCIE
				end
			end
		end
		device ref pcie_rp7 off end # PCIE7 no SD card
		device ref emmc on
			probe STORAGE STORAGE_UNKNOWN
			probe STORAGE STORAGE_EMMC
		end
		device ref ish on
			chip drivers/intel/ish
				register "add_acpi_dma_property" = "true"
				device generic 0 on end
			end
			probe STORAGE STORAGE_UNKNOWN
			probe STORAGE STORAGE_UFS
		end
		device ref ufs on
			probe STORAGE STORAGE_UNKNOWN
			probe STORAGE STORAGE_UFS
		end
		device ref pch_espi on
			chip ec/google/chromeec
				use conn0 as mux_conn[0]
				use conn1 as mux_conn[1]
				device pnp 0c09.0 on end
			end
		end
		device ref pmc hidden
			chip drivers/intel/pmc_mux
				device generic 0 on
					chip drivers/intel/pmc_mux/conn
						use usb2_port1 as usb2_port
						use tcss_usb3_port1 as usb3_port
						device generic 0 alias conn0 on end
					end
					chip drivers/intel/pmc_mux/conn
						use usb2_port2 as usb2_port
						use tcss_usb3_port2 as usb3_port
						device generic 1 alias conn1 on
							probe DB_USB DB_1C_1A
							probe DB_USB DB_1C_LTE
						end
					end
				end
			end
		end
		device ref tcss_xhci on
			chip drivers/usb/acpi
				device ref tcss_root_hub on
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Port C0 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
						device ref tcss_usb3_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Port C1 (DB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
						device ref tcss_usb3_port2 on end
					end
				end
			end
		end
		device ref xhci on
			chip drivers/usb/acpi
				device ref xhci_root_hub on
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Port C0 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
						device ref usb2_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Port C1 (DB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
						device ref usb2_port2 on
							probe DB_USB DB_1C_1A
							probe DB_USB DB_1C_LTE
						end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A0 (MLB)""
						register "type" = "UPC_TYPE_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
						device ref usb2_port3 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A1 (DB)""
						register "type" = "UPC_TYPE_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
						device ref usb2_port4 on
							probe DB_USB DB_1C_1A
						end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 WWAN""
						register "type" = "UPC_TYPE_INTERNAL"
						device ref usb2_port4 on
							probe DB_USB DB_1C_LTE
						end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Camera""
						register "type" = "UPC_TYPE_INTERNAL"
						device ref usb2_port6 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Bluetooth""
						register "type" = "UPC_TYPE_INTERNAL"
						register "reset_gpio" =
							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
						device ref usb2_port8 on
							probe WIFI_TYPE WIFI_PCIE
						end
					end
					chip drivers/usb/acpi
						register "desc" = ""CNVI Bluetooth""
						register "type" = "UPC_TYPE_INTERNAL"
						register "reset_gpio" =
							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
						device ref usb2_port10 on
							probe WIFI_TYPE WIFI_CNVI
						end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A0 (MLB)""
						register "type" = "UPC_TYPE_USB3_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
						device ref usb3_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A1 (DB)""
						register "type" = "UPC_TYPE_USB3_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
						device ref usb3_port2 on
							probe DB_USB DB_1C_1A
						end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 WWAN""
						register "type" = "UPC_TYPE_INTERNAL"
						device ref usb3_port2 on
							probe DB_USB DB_1C_LTE
						end
					end
				end
			end
		end
	end
end