aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/google/brya/variants/moli/overridetree.cb
blob: e9bc846ce85cfdcc035a2dc57ba2e1f9518ec09c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
fw_config
	field  DB_OPT	2	3
		option	OPT_ABSENT	0
		option	OPT_HDMI	1
		option	OPT_DP		2
	end
end
chip soc/intel/alderlake
	# Enable HDMI2 in PortA, HDMI1 in PortB, HDMI/DP in Port2
	register "ddi_ports_config" = "{
		[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
		[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
	}"
	register "usb2_ports[1]" = "USB2_PORT_EMPTY" 		# Disable USB2_Type-A Port A2
	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"  # USB2_Type-A Port A3
	register "usb2_ports[8]" = "USB2_PORT_EMPTY"	# Disable USB2_Type-A Port A9
	register "tcss_ports[2]" = "TCSS_PORT_EMPTY"	# Disable TCP3
	register "cnvi_bt_audio_offload" = "true"
	device domain 0 on
		device ref tcss_dma0 on
			chip drivers/intel/usb4/retimer
				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
				use tcss_usb3_port1 as dfp[0].typec_port
				device generic 0 on end
			end
		end
		device ref pcie4_0 on
		# Enable CPU PCIE RP 1 using CLK 0
			register "cpu_pcie_rp[CPU_RP(1)]" = "{
				.clk_req = 0,
				.clk_src = 0,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
		end # SSD gen4
		device ref cnvi_wifi on
			chip drivers/wifi/generic
				register "wake" = "GPE0_PME_B0"
				device generic 0 on end
			end
		end # WiFi
		device ref i2c0 on
			chip drivers/i2c/nau8825
				register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
				register "jkdet_enable" = "1"
				register "jkdet_pull_enable" = "0"
				register "jkdet_pull_up" = "0"
				register "jkdet_polarity" = "1"      # ActiveLow
				register "vref_impedance" = "2"      # 125kOhm
				register "micbias_voltage" = "6"     # 2.754
				register "sar_threshold_num" = "4"
				register "sar_threshold[0]" = "0x0C"
				register "sar_threshold[1]" = "0x1C"
				register "sar_threshold[2]" = "0x38"
				register "sar_threshold[3]" = "0x60"
				register "sar_hysteresis" = "1"
				register "sar_voltage" = "6"
				register "sar_compare_time" = "0"     # 500ns
				register "sar_sampling_time" = "0"    # 2us
				register "short_key_debounce" = "2"   # 100ms
				register "jack_insert_debounce" = "7" # 512ms
				register "jack_eject_debounce" = "7"  # 512ms
				device i2c 1a on end
			end
		end # Audio Nau8825
		device ref pcie_rp6 on
			# Enable PCIe-to-i225 bridge PCIe 6 using clk 5
			register "pch_pcie_rp[PCH_RP(6)]" = "{
				.clk_src = 5,
				.clk_req = 5,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
			device pci 00.0 on end
		end # IntelI225V Ethernet NIC
		device ref pcie_rp7 on
			chip drivers/net
				register "customized_leds" = "0x05af"
				register "wake" = "GPE0_DW0_07"
				register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H22)"
				register "stop_delay_ms" = "12" # NIC needs time to quiesce
				register "stop_off_delay_ms" = "1"
				register "has_power_resource" = "1"
				register "device_index" = "0"
				device pci 00.0 on end
			end
		end # RTL8111K Ethernet NIC
		device ref pcie_rp8 on
			chip soc/intel/common/block/pcie/rtd3
				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
				register "srcclk_pin" = "3"
				device generic 0 on end
			end
		end # PCIE8 SD card
		device ref pcie_rp9  off end        #pcie_rp     9  Empty
		device ref pcie_rp10 off end        #pcie_rp     10     Empty
		device ref pcie_rp11 off end        #pcie_rp   11   Empty
		device ref pcie_rp12 on
			chip soc/intel/common/block/pcie/rtd3
				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
				register "srcclk_pin" = "1"
				register "reset_delay_ms" = "50"
				register "enable_delay_ms" = "20"
				device generic 0 alias emmc_rtd3 on end
			end # Enable PCIe-to-eMMC bridge PCIE 12 using clk 1
			register "pch_pcie_rp[PCH_RP(12)]" = "{
				.clk_src = 1,
				.clk_req = 1,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
		end # PCIE12 BH799BB
		device ref pch_espi on
			chip ec/google/chromeec
				use conn0 as mux_conn[0]
				device pnp 0c09.0 on end
			end
		end
		device ref pmc hidden
			chip drivers/intel/pmc_mux
				device generic 0 on
					chip drivers/intel/pmc_mux/conn
						use usb2_port1 as usb2_port
						use tcss_usb3_port1 as usb3_port
						device generic 0 alias conn0 on end
					end
				end
			end
		end
		device ref tcss_xhci on
			chip drivers/usb/acpi
				device ref tcss_root_hub on
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Port C0 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
						device ref tcss_usb3_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Port C2 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
						device ref tcss_usb3_port2 on end
					end
				end
			end
		end
		device ref xhci on
			chip drivers/usb/acpi
				device ref xhci_root_hub on
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Port C0 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
						device ref usb2_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Port C2 (MLB)""
						register "type" = "UPC_TYPE_A"
						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
						device ref usb2_port3 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A4 (MLB)""
						register "type" = "UPC_TYPE_A"
						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
						device ref usb2_port4 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 NFC""
						register "type" = "UPC_TYPE_INTERNAL"
						device ref usb2_port5 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A3 (MLB)""
						register "type" = "UPC_TYPE_A"
						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
						device ref usb2_port6 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A2 (MLB)""
						register "type" = "UPC_TYPE_A"
						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(6, 1))"
						device ref usb2_port7 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A1 (MLB)""
						register "type" = "UPC_TYPE_A"
						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 1))"
						device ref usb2_port8 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Bluetooth""
						register "type" = "UPC_TYPE_INTERNAL"
						register "reset_gpio" =	"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
						device ref usb2_port10 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A1 (MLB)""
						register "type" = "UPC_TYPE_USB3_A"
						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 2))"
						device ref usb3_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A2 (MLB)""
						register "type" = "UPC_TYPE_USB3_A"
						register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(6, 1))"
						device ref usb3_port2 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A3 (MLB)""
						register "type" = "UPC_TYPE_USB3_A"
						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
						device ref usb3_port3 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A4 (MLB)""
						register "type" = "UPC_TYPE_USB3_A"
						register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
						device ref usb3_port4 on end
					end
				end
			end
		end # USB2 and USB3 Port
	end

end