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chip soc/intel/broadwell
register "panel_cfg" = "{
.up_delay_ms = 40,
.down_delay_ms = 15,
.cycle_delay_ms = 400,
.backlight_on_delay_ms = 50,
.backlight_off_delay_ms = 210,
.backlight_pwm_hz = 200,
}"
device domain 0 on
chip soc/intel/broadwell/pch
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
device pci 1f.2 on end # SATA Controller
end
end
end
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