blob: de9c2131c35e27fbb7c0cb31e51b41a8c3a2831a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
|
##
## This file is part of the coreboot project.
##
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/intel/sandybridge
device cpu_cluster 0 on
chip cpu/intel/model_206ax
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"
device lapic 0 on end
device lapic 0xacac off end
end
end
register "pci_mmio_size" = "2048"
device domain 0 on
subsystemid 0x1458 0x5000 inherit
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PEG
device pci 02.0 on end # iGPU
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x003c0a01"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
device pci 16.0 on end # MEI #1
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # HD Audio
device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1_3)
device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1)
device pci 1c.2 off end # RP #3:
device pci 1c.3 off end # RP #4:
device pci 1c.4 on end # RP #4: Realtek RTL8111F GbE NIC
device pci 1c.5 on end # RP #5: PCIe x1 Port (PCIEX1_2)
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge
chip superio/ite/it8728f
device pnp 2e.0 off end # Floppy
device pnp 2e.1 off end # COM1
device pnp 2e.2 off end # COM2
device pnp 2e.3 off end # Parallel port
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x0a30
io 0x62 = 0x0a20
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
end
device pnp 2e.6 on end # Mouse
device pnp 2e.7 on # GPIO
irq 0x25 = 0x40
irq 0x26 = 0xf7
irq 0x27 = 0x10
irq 0x2c = 0x80
io 0x60 = 0x0000
io 0x62 = 0x0a00
io 0x64 = 0x0000
irq 0x73 = 0x00
irq 0xc1 = 0x37
irq 0xcb = 0x00
irq 0xf0 = 0x10
irq 0xf1 = 0x42
irq 0xf6 = 0x1c
end
device pnp 2e.a off end # CIR
end
end
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 on end # Thermal
end
end
end
|
