blob: d15c99e966cb4d1f2fe683e69392b035773fdd72 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Google Inc.
##
## This software is licensed under the terms of the GNU General Public
## License version 2, as published by the Free Software Foundation, and
## may be copied, distributed, and modified under those terms.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
# To execute, do:
# util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf
# qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf
if BOARD_EMULATION_QEMU_RISCV_RV64
config BOARD_EMULATION_QEMU_RISCV
def_bool y
select ARCH_RISCV_RV64
endif
if BOARD_EMULATION_QEMU_RISCV_RV32
config BOARD_EMULATION_QEMU_RISCV
def_bool y
select ARCH_RISCV_RV32
endif
if BOARD_EMULATION_QEMU_RISCV
config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_UCB_RISCV
select BOARD_ROMSIZE_KB_4096
select HAVE_UART_SPECIAL
select BOOT_DEVICE_NOT_SPI_FLASH
select MISSING_BOARD_RESET
config MAINBOARD_DIR
string
default emulation/qemu-riscv
config MAINBOARD_PART_NUMBER
string
default "QEMU RISCV"
config MAX_CPUS
int
default 1
config DRAM_SIZE_MB
int
default 32768
endif # BOARD_EMULATION_QEMU_RISCV
|
