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# SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge
register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
device domain 0x0 on
subsystemid 0x1028 0x04aa inherit
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "docking_supported" = "0"
register "pcie_port_coalesce" = "1"
register "usb_port_config" = "{
{ 1, 1, 0 },
{ 1, 1, 0 },
{ 1, 1, 1 },
{ 1, 1, 1 },
{ 1, 0, 2 }, // FIXME: Unknown current: RCBA(0x3510)=0x3510
{ 1, 0, 2 }, // FIXME: Unknown current: RCBA(0x3514)=0x3514
{ 1, 6, 3 },
{ 1, 6, 3 },
{ 1, 0, 5 }, // FIXME: Unknown current: RCBA(0x3520)=0x3520
{ 1, 6, 5 },
{ 1, 6, 5 },
{ 1, 0, 5 }, // FIXME: Unknown current: RCBA(0x352c)=0x352c
{ 1, 6, 6 },
{ 0, 6, 6 },
}"
device ref mei1 on end
device ref ehci2 on end
device ref pcie_rp1 on end
device ref pcie_rp4 on end
device ref pcie_rp5 on end
device ref ehci1 on end
device ref lpc on
register "gen1_dec" = "0x003c0a01"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
end
device ref sata1 on
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x1f"
end
device ref smbus on end
end
device ref host_bridge on end
device ref peg10 on end
end
end
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