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# This file is part of the coreboot project.
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
register "gfx.link_frequency_270_mhz" = "1"
register "gfx.ndid" = "3"
register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4"
register "gpu_dp_d_hotplug" = "4"
device cpu_cluster 0x0 on
chip cpu/intel/model_206ax # FIXME: check all registers
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"
device lapic 0x0 on end
device lapic 0xacac off end
end
end
device domain 0x0 on
device pci 00.0 on # Host bridge
subsystemid 0x8086 0x2010
end
device pci 01.0 on # PCIe Bridge for discrete graphics
subsystemid 0x8086 0x2010
end
device pci 01.1 on # PCIe Bridge for discrete graphics
subsystemid 0x8086 0x2010
end
device pci 02.0 on # Internal graphics VGA controller
subsystemid 0x8086 0x2211
end
subsystemid 0x8086 0x7270 inherit
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "1"
register "gen1_dec" = "0x0000164d"
register "gen2_dec" = "0x000c0681"
register "gen3_dec" = "0x000406f1"
register "gen4_dec" = "0x000c06a1"
register "gpi7_routing" = "2"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
# Intense PC SATA portmap:
# Port 0: internal 2.5" bay
# Port 1: optional FACE module
# Port 2: rear eSATA
# Port 3: rear eSATA
# Port 4: mSATA
# Port 5: optional FACE module
# enable ALL ports (FACE module REQUIRED for ports 1&5)
register "sata_port_map" = "0x3f"
# enable ONLY ports present on stock MintBox/Intense PC
#register "sata_port_map" = "0x1d"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
device pci 14.0 on end # USB 3.0 Controller
device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 on end # Intel Gigabit Ethernet
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #2
device pci 1c.2 on end # PCIe Port #3
device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 on end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1c.6 off end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on end # LPC bridge
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 on end # Thermal
end
end
end
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