blob: a1033ec3dfc5446606ad7013cd02b81979aef83b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
|
##
## This file is part of the coreboot project.
##
##
## SPDX-License-Identifier: GPL-2.0-only
if BOARD_CAVIUM_CN8100_SFF_EVB
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192
select COMMON_CBFS_SPI_WRAPPER
select RTC
select SOC_CAVIUM_CN81XX
select SPI_FLASH
select SPI_FLASH_STMICRO
select MISSING_BOARD_RESET
config MAINBOARD_DIR
string
default "cavium/cn8100_sff_evb"
config DRAM_SIZE_MB
int
default 8192
config BOOT_DEVICE_SPI_FLASH_BUS
int
default 0
config CONSOLE_SERIAL_UART_ADDRESS
hex
depends on DRIVERS_UART
default 0x87E028000000
config UART_FOR_CONSOLE
int
depends on DRIVERS_UART
default 0
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
config MAX_CPUS
default 4
##########################################################
#### Update below when adding a new derivative board. ####
##########################################################
config MAINBOARD_PART_NUMBER
string
default "CN8100_SFF_EVB"
endif
|
