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#
# This file is part of the coreboot project.
#
# Copyright (C) 2013 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
chip northbridge/amd/pi/00730F01/root_complex
device cpu_cluster 0 on
chip cpu/amd/pi/00730F01
device lapic 0 on end
end
end
device domain 0 on
subsystemid 0x1022 0x1410 inherit
chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 0.2 off end # IOMMU
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge
device pci 2.1 on end # x4 PCIe slot
device pci 2.2 on end # PCIe Q7 Realtek GBit LAN
device pci 2.3 on end # PCIe CB Realtek GBit LAN
device pci 2.4 on end # PCIe x2 BAP FPGA
device pci 8.0 on end # Platform Security Processor
end #chip northbridge/amd/pi/00730F01
chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
device pci 10.0 on end # XHCI HC0
device pci 11.0 on end # SATA
device pci 12.0 on end # EHCI #0
device pci 13.0 on end # EHCI #1
device pci 14.0 on end # SMBus
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/fintek/f81866d
register "hwm_amd_tsi_addr" = "0x98" # Set to AMD
register "hwm_amd_tsi_control" = "0x02" # Set to AMD
register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM
register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode
register "hwm_fan3_control" = "0x00" # Fan control 23kHz
register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz
register "hwm_fan2_bound1" = "0x3C" # 60°C
register "hwm_fan2_bound2" = "0x32" # 50°C
register "hwm_fan2_bound3" = "0x28" # 40°C
register "hwm_fan2_bound4" = "0x1E" # 30°C
register "hwm_fan2_seg1_speed" = "0xFF" # 100%
register "hwm_fan2_seg2_speed" = "0xD9" # 85%
register "hwm_fan2_seg3_speed" = "0xB2" # 70%
register "hwm_fan2_seg4_speed" = "0x99" # 60%
register "hwm_fan2_seg5_speed" = "0x80" # 50%
register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor
device pnp 4e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 4e.3 off end # Parallel Port
device pnp 4e.4 on # Hardware Monitor
io 0x60 = 0x295
irq 0x70 = 0
end
device pnp 4e.5 off # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 4e.6 off end # GPIO
device pnp 4e.7 on end # WDT
device pnp 4e.a off end # PME
device pnp 4e.10 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.11 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 4e.12 off # COM3
io 0x60 = 0x3e8
irq 0x70 = 4
end
device pnp 4e.13 off # COM4
io 0x60 = 0x2e8
irq 0x70 = 3
end
device pnp 4e.14 off # COM5
end
device pnp 4e.15 off # COM6
end
end # f81866d
end #LPC
device pci 14.7 on end # SD
end #chip southbridge/amd/pi/hudson
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
end #domain
end #northbridge/amd/pi/00730F01/root_complex
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