blob: 57ec653c0eff24ece02fbd05dbdb4cb1ce8c2954 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
|
##
## This file is part of the coreboot project.
##
##
## This program is free software: you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation, either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/intel/sandybridge
device cpu_cluster 0x0 on
chip cpu/intel/model_206ax
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"
device lapic 0x0 on end
device lapic 0xacac off end
end
end
device domain 0x0 on
subsystemid 0x1043 0x844d inherit
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PCIe Bridge for discrete graphics
device pci 02.0 on end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x000c0291"
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on # High Definition Audio Audio controller
subsystemid 0x1043 0x8445
end
device pci 1c.0 off end # PCIe Port #1
device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 on end # PCIe x1 Slot 1 PCIE_1
device pci 1c.4 on end # PCIe x1 Slot 2 PCIE_2
device pci 1c.5 on # Realtek Gigabit NIC
device pci 00.0 on end
end
device pci 1c.6 off end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge PCI-LPC bridge
chip superio/nuvoton/nct6779d
device pnp 2e.1 off end # Parallel
device pnp 2e.2 off end # UART A
device pnp 2e.3 off end # UART B, IR
device pnp 2e.5 on # Keyboard
io 0x60 = 0x0060
io 0x62 = 0x0064
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GPIO6-8
device pnp 2e.8 off end # WDT1, GPIO0, GPIO1
device pnp 2e.108 off end # GPIO0
device pnp 2e.9 off end # GPIO1-8
device pnp 2e.109 on end # GPIO1
device pnp 2e.209 on end # GPIO2
device pnp 2e.309 on end # GPIO3
device pnp 2e.409 off end # GPIO4
device pnp 2e.509 on end # GPIO5
device pnp 2e.609 off end # GPIO6
device pnp 2e.709 off end # GPIO7
device pnp 2e.a off end # ACPI
device pnp 2e.b on # H/W Monitor, FP LED
io 0x60 = 0x0290
io 0x62 = 0
irq 0x70 = 0
end
device pnp 2e.d off end # WDT1
device pnp 2e.e off end # CIR WAKE-UP
device pnp 2e.f off end # GPIO Push-pull/Open-drain selection
device pnp 2e.14 off end # PORT80 UART
device pnp 2e.16 off end # Deep Sleep
end
end
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 off end # Thermal
end
end
end
|
