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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#ifndef _GPIO_DVS_H
#define _GPIO_DVS_H
#include <soc/gpe.h>
#include <soc/gpio.h>
#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \
_PAD_CFG_STRUCT(val, config0, config1)
/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
/* GPIO Group GPP_A */
H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */
H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */
H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */
H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */
H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */
H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */
H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */
H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */
H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */
H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */
H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN# */
H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */
H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */
H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */
/* GPIO Group GPP_B */
H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */
H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */
H110_PAD_DW0_DW1_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */
H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */
H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */
/* GPIO Group GPP_C */
H110_PAD_DW0_DW1_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */
H110_PAD_DW0_DW1_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */
H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */
H110_PAD_DW0_DW1_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */
H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */
/* GPP_C6 - RESERVED */
/* GPP_C7 - RESERVED */
H110_PAD_DW0_DW1_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */
H110_PAD_DW0_DW1_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */
H110_PAD_DW0_DW1_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */
H110_PAD_DW0_DW1_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */
H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */
H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */
H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */
H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */
/* GPIO Group GPP_D */
H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */
H110_PAD_DW0_DW1_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */
H110_PAD_DW0_DW1_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */
H110_PAD_DW0_DW1_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */
H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */
H110_PAD_DW0_DW1_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */
H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */
/* GPIO Group GPP_E */
H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */
H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */
H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */
H110_PAD_DW0_DW1_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */
/* SATA_DEVSLP0 */
H110_PAD_DW0_DW1_CFG(GPP_E4, 0x84000500, 0x0000001c),
/* SATA_DEVSLP1 */
H110_PAD_DW0_DW1_CFG(GPP_E5, 0x84000500, 0x0000001d),
/* SATA_DEVSLP2 */
H110_PAD_DW0_DW1_CFG(GPP_E6, 0x84000500, 0x0000001e),
H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */
H110_PAD_DW0_DW1_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */
H110_PAD_DW0_DW1_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */
H110_PAD_DW0_DW1_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */
H110_PAD_DW0_DW1_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */
/* GPIO Group GPP_F */
H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */
H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */
H110_PAD_DW0_DW1_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */
H110_PAD_DW0_DW1_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */
H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */
/* GPIO Group GPP_G */
H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */
H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */
/* GPIO Group GPP_H */
H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */
/* GPIO Group GPD */
H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */
H110_PAD_DW0_DW1_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */
H110_PAD_DW0_DW1_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */
H110_PAD_DW0_DW1_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */
H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */
H110_PAD_DW0_DW1_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */
H110_PAD_DW0_DW1_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */
H110_PAD_DW0_DW1_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */
H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */
/* GPIO Group GPP_I */
H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */
H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */
H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */
H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */
H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */
/* DDPB_CTRLCLK */
H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072),
/* DDPB_CTRLDATA */
H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00001073),
/* DDPC_CTRLCLK */
H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074),
/* DDPC_CTRLDATA */
H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075),
/* DDPD_CTRLCLK */
H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076),
/* DDPD_CTRLDATA */
H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077),
};
/* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = {
/* GPIO Group GPP_A */
H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */
H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */
H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */
H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */
H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */
H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */
H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */
H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */
H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */
H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */
/* ---- */
/* SUSWARN#/SUSPWRDNACK */
H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025),
H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */
H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */
};
#endif
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