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path: root/src/mainboard/arima/hdama/Config.lb
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##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
	default ROM_SECTION_SIZE   = FALLBACK_SIZE
	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
	default ROM_SECTION_OFFSET = 0
end

##
## Compute the start location and size size of
## The linuxBIOS bootloader.
##
default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_STREAM     = 1

##
## Compute where this copy of linuxBIOS will start in the boot rom
##
default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )

##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )

# sample config for arima/hdama
chip northbridge/amd/amdk8
	print "HI MOM!\n"
	device pnp cf8.0 on					# cf8 config
	print "HI MOM!\n"
		device pci 18.0 on				#  northbridge 
	print "HI MOM!\n"
			#  devices on link 0, link 0 == LDT 0 
			chip southbridge/amd/amd8131
			print "SOUTH\n"
				# the on/off keyword is mandatory
				device pci 0.0 on end
			print "SOUTH2\n"
				device pci 0.1 on end
			print "SOUTH3\n"
				device pci 1.0 on end
			print "SOUTH4\n"
				device pci 1.1 on end
			end
			chip southbridge/amd/amd8111
				print "NEXT SOUTH\n"
				# this "device pci 0.0" is the parent the next one
				# PCI bridge
				device pci 0.0 on
					# this "device pci 0.0" is a child of the
					# previous one
					# devices behind the bridge
					device pci 0.0 on end
					device pci 0.1 on end
					device pci 0.2 on end
					# the device statement can span across multiple
					# lines too
					device pci 1.0
						off
					end
				end
				device pci 1.0 on
					chip superio/NSC/pc87360
						device pnp 2e.3 on
							io 0x60 = 0x3f8
							irq 0x70 = 4
						end 
					end
				end
				device pci 1.1 on end
				device pci 1.2 off end
				device pci 1.3 off end
				device pci 1.5 on end
				device pci 1.6 on end
			end
		end #  device pci 18.0 
		device pci 18.0 on
			#  some non-existence devices on link 1 
		end
		device pci 18.0 on
			#  some non-existence devices on link 2 
		end
		device pci 18.1
			#  empty 
		end
		device pci 18.2
			#  empty 
		end
		device pci 18.3
			#  empty 
		end
	end #  device pnp 
end