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## SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/alderlake
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "pmc_gpe0_dw0" = "GPP_B"
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
register "sagv" = "SaGv_Enabled"
register "dptf_enable" = "1"
register "s0ix_enable" = "true"
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
},
}"
# Configure external V1P05/Vnn/VnnSx Rails
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
.v1p05_voltage_mv = 1050,
.vnn_voltage_mv = 780,
.vnn_sx_voltage_mv = 1050,
.v1p05_icc_max_ma = 500,
.vnn_icc_max_ma = 500,
}"
device domain 0 on
device ref igpu on
register "ddi_portA_config" = "1"
register "ddi_portB_config" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
end
device ref dtt on end
device ref crashlog off end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)" # USB3/2 Type A upper
end
device ref xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC0), /* Type-C */
[1] = USB2_PORT_MID(OC_SKIP), /* microSD card reader */
[2] = USB2_PORT_MID(OC3), /* USB2 Type A upper */
[3] = USB2_PORT_MID(OC3), /* USB2 Type A lower */
[4] = USB2_PORT_MID(OC3), /* USB3/2 Type A upper */
[5] = USB2_PORT_MID(OC3), /* USB3/2 Type A lower */
[7] = USB2_PORT_MID(OC_SKIP), /* M.2 WLAN */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), /* Type-C */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* microSD card reader */
[5] = USB3_PORT_DEFAULT(OC3), /* USB3/2 Type A lower */
[6] = USB3_PORT_DEFAULT(OC3), /* USB3/2 Type A upper */
}"
end
device ref cnvi_wifi on
register "cnvi_bt_core" = "true"
register "cnvi_bt_audio_offload" = "true"
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref i2c0 on
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
end
device ref i2c1 on
register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
end
device ref i2c2 on
register "serial_io_i2c_mode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
end
device ref i2c3 on
register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
end
device ref sata on
register "sata_salp_support" = "1"
register "sata_ports_enable" = "{
[0] = 1,
[1] = 1,
}"
register "sata_ports_dev_slp" = "{
[0] = 1,
[1] = 1,
}"
end
device ref i2c5 on
register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
end
device ref pcie_rp3 on
register "pch_pcie_rp[PCH_RP(3)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_CLK_REQ_DETECT,
}"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
"M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth2X"
end
device ref pcie_rp7 on # LAN1
register "pch_pcie_rp[PCH_RP(7)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_CLK_REQ_DETECT,
}"
end
device ref pcie_rp9 on # LAN2
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_CLK_REQ_DETECT,
}"
end
device ref pcie_rp10 on
register "pch_pcie_rp[PCH_RP(10)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_CLK_REQ_DETECT,
}"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
"M.2/E 2230 (M2_WIFI1)" "SlotDataBusWidth1X"
end
device ref pch_espi on
# Needed for ITE SuperIO
register "gen1_dec" = "0x00fc0201"
register "gen2_dec" = "0x007c0a01"
register "gen3_dec" = "0x000c03e1"
register "gen4_dec" = "0x001c02e1"
chip superio/ite/it8613e
register "TMPIN1.mode" = "THERMAL_RESISTOR"
register "ec.vin_mask" = "VIN_ALL"
# CPU_FAN1
register "FAN2.mode" = "FAN_SMART_AUTOMATIC"
register "FAN2.smart.tmpin" = " 1"
register "FAN2.smart.tmp_off" = "32" # Vendor default: 30
register "FAN2.smart.tmp_start" = "35"
register "FAN2.smart.tmp_full" = "96"
register "FAN2.smart.tmp_delta" = " 1" # Vendor default: 2
register "FAN2.smart.pwm_start" = "30" # Vendor default: 40
register "FAN2.smart.slope" = " 1"
# SYSFANCN1
register "FAN3.mode" = "FAN_SMART_SOFTWARE"
register "FAN3.smart.pwm_start" = "80"
# SYS_FAN1
register "FAN4.mode" = "FAN_SMART_SOFTWARE"
register "FAN4.smart.pwm_start" = "127"
device pnp 2e.0 off end # Floppy
device pnp 2e.1 off end # COM 1
device pnp 2e.4 on # Environment Controller
io 0x60 = 0xa30
io 0x62 = 0xa20
irq 0x70 = 0x00
end
device pnp 2e.5 off end # Keyboard
device pnp 2e.6 off end # Mouse
device pnp 2e.7 on # GPIO
io 0x60 = 0x000
io 0x62 = 0xa00
irq 0x70 = 0x00
irq 0x71 = 0x01
end
device pnp 2e.a off end # CIR
end
end
device ref uart0 on
register "serial_io_uart_mode" = "{
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
}"
end
device ref gspi0 on
register "serial_io_gspi_mode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoPci,
}"
end
device ref ish on end
device ref hda on
register "pch_hda_dsp_enable" = "1"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_codec_enable" = "1"
end
device ref smbus on end
end
end
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