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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#define ONE_MB 0x100000
//#define SMBUS_IO_BASE 0x6000
void set_pcie_reset(void);
void set_pcie_dereset(void);
/**
* TODO
* SB CIMx callback
*/
void set_pcie_reset(void)
{
}
/**
* TODO
* mainboard specific SB CIMx callback
*/
void set_pcie_dereset(void)
{
}
/*************************************************
* enable the dedicated function in torpedo board.
*************************************************/
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev);
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};
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