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## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/failovercalculation.lb
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
#dir /drivers/si/3114
#needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o
if CONFIG_GENERATE_MP_TABLE
object mptable.o
end
if CONFIG_GENERATE_PIRQ_TABLE
object irq_tables.o
end
#if CONFIG_GENERATE_ACPI_TABLES
# object acpi_tables.o
# object fadt.o
# if CONFIG_SB_HT_CHAIN_ON_BUS0
# object dsdt_bus0.o
# else
# object dsdt.o
# end
# object ssdt.o
# if CONFIG_ACPI_SSDTX_NUM
# if CONFIG_SB_HT_CHAIN_ON_BUS0
# object ssdt2_bus0.o
# else
# object ssdt2.o
# end
# end
#end
if CONFIG_GENERATE_ACPI_TABLES
object acpi_tables.o
object fadt.o
makerule dsdt.c
depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
action "mv dsdt_lb.hex dsdt.c"
end
object ./dsdt.o
#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
if CONFIG_ACPI_SSDTX_NUM
makerule ssdt2.c
depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
action "mv pci2.hex ssdt2.c"
end
object ./ssdt2.o
makerule ssdt3.c
depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
action "mv pci3.hex ssdt3.c"
end
object ./ssdt3.o
makerule ssdt4.c
depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
action "mv pci4.hex ssdt4.c"
end
object ./ssdt4.o
end
end
if CONFIG_USE_INIT
# compile cache_as_ram.c to auto.o
makerule ./cache_as_ram_auto.o
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
if CONFIG_USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
makerule ./apc_auto.o
depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
end
ldscript /arch/i386/init/ldscript_apc.lb
end
end
##
## Build our 16 bit and 32 bit coreboot entry code
##
if CONFIG_HAVE_FAILOVER_BOOT
if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
else
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
end
mainboardinit cpu/x86/32bit/entry32.inc
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
##
## Build our reset vector (This is where coreboot is entered)
##
if CONFIG_HAVE_FAILOVER_BOOT
if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
else
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
end
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if CONFIG_HAVE_FAILOVER_BOOT
if CONFIG_USE_FAILOVER_IMAGE
ldscript /arch/i386/lib/failover_failover.lds
end
else
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
##
## Include the secondary Configuration files
##
config chip.h
# sample config for amd/serengeti_cheetah
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
chip cpu/amd/socket_F
device apic 0 on end
end
end
device pci_domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0
chip southbridge/amd/amd8132
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent the next one
# PCI bridge
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 off end
device pci 1.0 off end
end
device pci 1.0 on
chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1.1 on end
device pci 1.2 on end
device pci 1.3 on
chip drivers/i2c/i2cmux # pca9556 smbus mux
device i2c 18 on #0 pca9516 1
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
end
end
device i2c 18 on #1 pca9516 2
chip drivers/generic/generic #dimm 1-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 1-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 1-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 1-1-1
device i2c 53 on end
end
chip drivers/generic/generic #dimm 1-2-0
device i2c 54 on end
end
chip drivers/generic/generic #dimm 1-2-1
device i2c 55 on end
end
chip drivers/generic/generic #dimm 1-3-0
device i2c 56 on end
end
chip drivers/generic/generic #dimm 1-3-1
device i2c 57 on end
end
end
end
end # acpi
device pci 1.5 off end
device pci 1.6 off end
register "ide0_enable" = "1"
register "ide1_enable" = "1"
end
end # device pci 18.0
device pci 18.0 on end
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end
chip northbridge/amd/amdk8
device pci 19.0 on # northbridge
chip southbridge/amd/amd8151
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 1.0 on end
end
end # device pci 19.0
device pci 19.0 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
end #pci_domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 off end # mem
# device pnp 0.3 off end # cpuid
# device pnp 0.4 off end # smbus_regs_all
# device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# end
end
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