1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
|
# SPDX-License-Identifier: GPL-2.0-only
# TODO: Update for birman
chip soc/amd/phoenix
register "common_config.espi_config" = "{
.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
.generic_io_range[0] = {
.base = 0x3f8,
.size = 8,
},
.generic_io_range[1] = {
.base = 0x600,
.size = 256,
},
.io_mode = ESPI_IO_MODE_QUAD,
.op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
.crc_check_enable = 1,
.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
.periph_ch_en = 1,
.vw_ch_en = 1,
.oob_ch_en = 1,
.flash_ch_en = 0,
}"
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
GPIO_I2C2_SCL | GPIO_I2C3_SCL"
register "i2c[0].early_init" = "1"
register "i2c[1].early_init" = "1"
register "i2c[2].early_init" = "1"
register "i2c[3].early_init" = "1"
# I2C Pad Control RX Select Configuration
register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V"
register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V"
register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V"
register "s0ix_enable" = "true"
register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works<
device domain 0 on
device ref iommu on end
device ref gpp_bridge_1_1 on end # MXM
device ref gpp_bridge_1_2 on
# Required so the NVMe gets placed into D3 when entering S0i3.
chip drivers/pcie/rtd3/device
register "name" = ""NVME""
device pci 00.0 on end
end
end # NVMe SSD1
device ref gpp_bridge_1_3 on end # GBE
device ref gpp_bridge_2_1 on end # SD
device ref gpp_bridge_2_2 on end # WWAN
device ref gpp_bridge_2_3 on end # WIFI
device ref gpp_bridge_2_4 on
# Required so the NVMe gets placed into D3 when entering S0i3.
chip drivers/pcie/rtd3/device
register "name" = ""NVME""
device pci 00.0 on end
end
end # NVMe SSD0
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
device ref crypto on end # Crypto Coprocessor
device ref xhci_0 on # USB 3.1 (USB0)
chip drivers/usb/acpi
device ref xhci_0_root_hub on
chip drivers/usb/acpi
device ref usb3_port2 on end
end
chip drivers/usb/acpi
device ref usb3_port3 on end
end
chip drivers/usb/acpi
device ref usb2_port2 on end
end
chip drivers/usb/acpi
device ref usb2_port3 on end
end
chip drivers/usb/acpi
device ref usb2_port4 on end
end
chip drivers/usb/acpi
device ref usb2_port5 on end
end
chip drivers/usb/acpi
device ref usb2_port6 on end
end
end
end
end
device ref xhci_1 on # USB 3.1 (USB1)
chip drivers/usb/acpi
device ref xhci_1_root_hub on
chip drivers/usb/acpi
device ref usb3_port7 on end
end
chip drivers/usb/acpi
device ref usb2_port7 on end
end
end
end
end
device ref acp on end # Audio Processor (ACP)
end
device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
device ref usb4_xhci_0 on
chip drivers/usb/acpi
device ref usb4_xhci_0_root_hub on
chip drivers/usb/acpi
device ref usb3_port0 on end
end
chip drivers/usb/acpi
device ref usb2_port0 on end
end
end
end
end
device ref usb4_xhci_1 on
chip drivers/usb/acpi
device ref usb4_xhci_1_root_hub on
chip drivers/usb/acpi
device ref usb3_port1 on end
end
chip drivers/usb/acpi
device ref usb2_port1 on end
end
end
end
end
end
end
device ref i2c_0 on end
device ref i2c_1 on end
device ref i2c_2 on end
device ref i2c_3 on end
device ref uart_0 on end # UART0
end
|
