blob: 0b44109f9fe73d21ad3e75dc6a14ef8fe5f31f3d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
|
#ifndef DEVICE_HYPERTRANSPORT_DEF_H
#define DEVICE_HYPERTRANSPORT_DEF_H
#define HT_FREQ_200Mhz 0
#define HT_FREQ_300Mhz 1
#define HT_FREQ_400Mhz 2
#define HT_FREQ_500Mhz 3
#define HT_FREQ_600Mhz 4
#define HT_FREQ_800Mhz 5
#define HT_FREQ_1000Mhz 6
#define HT_FREQ_1200Mhz 7
#define HT_FREQ_1400Mhz 8
#define HT_FREQ_1600Mhz 9
#define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */
#endif /* DEVICE_HYPERTRANSPORT_DEF_H */
|