summaryrefslogtreecommitdiff
path: root/src/drivers/net/phy/m88e1512/m88e1512.c
blob: a8d1c730a18244e994056326b0dc75b366ceaf5a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
/* SPDX-License-Identifier: GPL-2.0-only */

#include <console/console.h>
#include <device/device.h>
#include <device/mdio.h>
#include <device/pci.h>
#include "chip.h"
#include "m88e1512.h"

static void switch_page(struct device *dev, uint8_t page)
{
	mdio_write(dev, PAGE_REG, page);
}

static void m88e1512_init(struct device *dev)
{
	struct drivers_net_phy_m88e1512_config *config = dev->chip_info;
	uint16_t reg;

	/* Configure LEDs if requested. */
	if (config->configure_leds) {
		printk(BIOS_DEBUG, "%s: Set a customized LED mode for %s.\n",
				dev_path(dev->bus->dev), dev->chip_ops->name);

		/* Select page 3 to access LED function control register. */
		switch_page(dev, 3);

		/* Modify PHY LED mode. */
		reg = mdio_read(dev, LED_FUNC_CTRL_REG);
		clrsetbits16(&reg, LED_FUNC_CTRL_MASK, config->led_0_ctrl |
				(config->led_1_ctrl << 4) | (config->led_2_ctrl << 8));
		mdio_write(dev, LED_FUNC_CTRL_REG, reg);

		/* Switch back to page 0. */
		switch_page(dev, 0);
	}

	/* INTn can be routed to LED[2] pin. */
	if (config->enable_int) {
		printk(BIOS_DEBUG, "%s: INTn is routed to LED[2] pin %s.\n",
				dev_path(dev->bus->dev), dev->chip_ops->name);

		/* Select page 3 to access LED function control register. */
		switch_page(dev, 3);

		reg = mdio_read(dev, LED_TIMER_CTRL_REG);
		setbits16(&reg, LED_IRQ_ENABLE);
		mdio_write(dev, LED_TIMER_CTRL_REG, reg);

		/* Switch back to page 0. */
		switch_page(dev, 0);
	}
}

struct device_operations m88e1512_ops = {
	.read_resources = noop_read_resources,
	.set_resources  = noop_set_resources,
	.init           = m88e1512_init,
};

struct chip_operations drivers_net_phy_m88e1512_ops = {
	CHIP_NAME("88E1512")
};