blob: 75d268723bbe4eeabf7abd149491d7d23110e80b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
|
##
## This file is part of the coreboot project.
##
## Copyright 2013 Google Inc.
## Copyright 2016-2017 secunet Security Networks AG
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config INTEL_DDI
bool
default n
help
helper functions for intel DDI operations
config INTEL_EDID
bool
default n
config INTEL_INT15
bool
default n
config INTEL_GMA_ACPI
bool
default n
config INTEL_GMA_SSC_ALTERNATE_REF
bool
default n
help
Set when the SSC reference clock for LVDS runs at a different fre-
quency than the general display reference clock.
To be set by northbridge or mainboard Kconfig. For most platforms,
there is no choice, i.e. for i945 and gm45 the SSC reference always
differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz
DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and newer, it's
the same frequency for SSC/non-SSC (120MHz). The only, currently
supported platform with a choice seems to be Pineview, where the
alternative is 100MHz vs. the default 96MHz.
config INTEL_GMA_SWSMISCI
bool
default n
help
Select this option for Atom-based platforms which use the SWSMISCI
register (0xe0) rather than the SWSCI register (0xe8).
config INTEL_GMA_LIBGFXINIT_EDID
bool
config GFX_GMA_ANALOG_I2C_HDMI_B
bool
config GFX_GMA_ANALOG_I2C_HDMI_C
bool
config GFX_GMA_ANALOG_I2C_HDMI_D
bool
config GFX_GMA
def_bool y
depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \
|| NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \
|| NORTHBRIDGE_INTEL_HASWELL \
|| SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \
|| SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \
|| SOC_INTEL_WHISKEYLAKE
depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID
select RAMSTAGE_LIBHWBASE
config GFX_GMA_INTERNAL_IS_EDP
bool
depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT
default n if GFX_GMA_INTERNAL_IS_LVDS
default y
config GFX_GMA_INTERNAL_IS_LVDS
bool
depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT
default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_NEHALEM
default n
if GFX_GMA
config GFX_GMA_DYN_CPU
def_bool y
help
Activates runtime CPU detection in libgfxinit.
config GFX_GMA_GENERATION
string
default "Broxton" if SOC_INTEL_APOLLOLAKE
default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \
SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL
default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE
default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X
config GFX_GMA_INTERNAL_PORT
string
default "DP" if GFX_GMA_INTERNAL_IS_EDP
default "LVDS"
config GFX_GMA_ANALOG_I2C_PORT
string
default "PCH_HDMI_B" if GFX_GMA_ANALOG_I2C_HDMI_B
default "PCH_HDMI_C" if GFX_GMA_ANALOG_I2C_HDMI_C
default "PCH_HDMI_D" if GFX_GMA_ANALOG_I2C_HDMI_D
default "PCH_DAC"
help
Boards with a DVI-I connector share the I2C pins for both analog and
digital displays. In that case, the EDID for a VGA display has to be
read over the I2C interface of the coupled digital port.
endif
|
