blob: ca0143d86c8bd81e0601c5ee58d4435fa21ba1cb (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
|
## SPDX-License-Identifier: GPL-2.0-only
config INTEL_DDI
bool
default n
help
helper functions for intel DDI operations
config INTEL_EDID
bool
default n
config INTEL_INT15
bool
default n
config INTEL_GMA_ACPI
bool
default n
config INTEL_GMA_BCLV_OFFSET
hex
default 0xc8254
config INTEL_GMA_BCLV_WIDTH
int
default 16
config INTEL_GMA_BCLM_OFFSET
hex
default 0xc8256
config INTEL_GMA_BCLM_WIDTH
int
default 16
config INTEL_GMA_SSC_ALTERNATE_REF
bool
default n
help
Set when the SSC reference clock for LVDS runs at a different fre-
quency than the general display reference clock.
To be set by northbridge or mainboard Kconfig. For most platforms,
there is no choice, i.e. for i945 and gm45 the SSC reference always
differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz
DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Arrandale and newer, it's
the same frequency for SSC/non-SSC (120MHz). The only, currently
supported platform with a choice seems to be Pineview, where the
alternative is 100MHz vs. the default 96MHz.
config INTEL_GMA_SWSMISCI
bool
default n
help
Select this option for Atom-based platforms which use the SWSMISCI
register (0xe0) rather than the SWSCI register (0xe8).
config INTEL_GMA_LIBGFXINIT_EDID
bool
config VBT_CBFS_COMPRESSION_DEFAULT_LZ4
def_bool n
help
Set LZ4 VBT compression.
config VBT_CBFS_COMPRESSION_DEFAULT_NONE
def_bool n
help
Disable VBT compression.
choice
prompt "VBT Compression algorithm"
default VBT_CBFS_COMPRESSION_LZ4 if VBT_CBFS_COMPRESSION_DEFAULT_LZ4
default VBT_CBFS_COMPRESSION_NONE if VBT_CBFS_COMPRESSION_DEFAULT_NONE
default VBT_CBFS_COMPRESSION_LZMA
config VBT_CBFS_COMPRESSION_LZMA
bool "Compress VBT with LZMA algorithm"
config VBT_CBFS_COMPRESSION_LZ4
bool "Compress VBT with LZ4 algorithm"
config VBT_CBFS_COMPRESSION_NONE
bool "Do not compress VBT"
endchoice
config VBT_CBFS_COMPRESSION_ALGORITHM
string
default "lzma" if VBT_CBFS_COMPRESSION_LZMA
default "lz4" if VBT_CBFS_COMPRESSION_LZ4
default "none" if VBT_CBFS_COMPRESSION_NONE
config GFX_GMA_ANALOG_I2C_HDMI_B
bool
config GFX_GMA_ANALOG_I2C_HDMI_C
bool
config GFX_GMA_ANALOG_I2C_HDMI_D
bool
config GFX_GMA_IGNORE_PRESENCE_STRAPS
def_bool n
depends on MAINBOARD_HAS_LIBGFXINIT
help
libgfxinit uses the GPU presence straps to determine if a display port
is present/enabled. Select this option if a board doesn't correctly implement
these straps, causing libgfxinit to fail to detect an attached panel.
config GFX_GMA
def_bool y
depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \
|| NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \
|| NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL \
|| SOC_INTEL_COMMON_SKYLAKE_BASE || SOC_INTEL_APOLLOLAKE \
|| SOC_INTEL_CANNONLAKE_BASE
depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID
select RAMSTAGE_LIBHWBASE
config EARLY_GFX_GMA
def_bool y
depends on SOC_INTEL_ALDERLAKE
depends on MAINBOARD_USE_EARLY_LIBGFXINIT
select ROMSTAGE_LIBHWBASE
config GFX_GMA_DEFAULT_MMIO
hex
depends on HWBASE_STATIC_MMIO && (GFX_GMA || EARLY_GFX_GMA)
help
Graphics device MMIO address. This is typically an unused
memory mapping region which can be allocated to the MMIO
region as graphics PCI device Base Address Range zero.
config GFX_GMA_PANEL_1_ON_EDP
bool
depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT \
|| MAINBOARD_HAS_EARLY_LIBGFXINIT
default n if GFX_GMA_PANEL_1_ON_LVDS
default y
config GFX_GMA_PANEL_1_ON_LVDS
bool
depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT \
|| MAINBOARD_HAS_EARLY_LIBGFXINIT
default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_IRONLAKE
default n
config INTEL_GMA_OPREGION_2_1
bool
default n
config INTEL_GMA_VERSION_2
bool
default n
help
Intel display port and pipe related register definitions have changed since
Tiger Lake SoC. This option enables support for the updated `TRANS_DDI_FUNC_CTL`
register definitions.
SoCs that support Intel GMA Version 2 include:
* Alder Lake
* Meteor Lake
* Tiger Lake
If you are unsure whether your SoC supports Intel GMA Version 2, it is safe to
disable this option.
if GFX_GMA || EARLY_GFX_GMA
config GFX_GMA_DYN_CPU
def_bool y
help
Activates runtime CPU detection in libgfxinit.
config GFX_GMA_GENERATION
string
default "Broxton" if SOC_INTEL_APOLLOLAKE
default "Skylake" if SOC_INTEL_COMMON_SKYLAKE_BASE || SOC_INTEL_CANNONLAKE_BASE
default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL
default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE
default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X
default "Tigerlake" if SOC_INTEL_ALDERLAKE
config GFX_GMA_PCH
string
default "Ibex_Peak" if NORTHBRIDGE_INTEL_IRONLAKE
default "Cougar_Point" if NORTHBRIDGE_INTEL_SANDYBRIDGE
default "Lynx_Point" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL
default "Sunrise_Point" if SOC_INTEL_COMMON_SKYLAKE_BASE
default "Cannon_Point" if SOC_INTEL_CANNONLAKE_BASE
default "Alder_Point" if SOC_INTEL_ALDERLAKE
default "No_PCH"
config GFX_GMA_PANEL_1_PORT
string
default "eDP" if GFX_GMA_PANEL_1_ON_EDP
default "LVDS"
config GFX_GMA_PANEL_2_PORT
string
default "Disabled"
config GFX_GMA_ANALOG_I2C_PORT
string
default "PCH_HDMI_B" if GFX_GMA_ANALOG_I2C_HDMI_B
default "PCH_HDMI_C" if GFX_GMA_ANALOG_I2C_HDMI_C
default "PCH_HDMI_D" if GFX_GMA_ANALOG_I2C_HDMI_D
default "PCH_DAC"
help
Boards with a DVI-I connector share the I2C pins for both analog and
digital displays. In that case, the EDID for a VGA display has to be
read over the I2C interface of the coupled digital port.
endif
|
