blob: 4c79b239b6614a4ae32a5cb7ca90aa557e743448 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config CPU_INTEL_FSP_MODEL_406DX
bool
if CPU_INTEL_FSP_MODEL_406DX
config CPU_SPECIFIC_OPTIONS
def_bool y
select PLATFORM_USES_FSP1_0
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC
select SUPPORT_CPU_UCODE_IN_CBFS
select PARALLEL_CPU_INIT
select TSC_SYNC_MFENCE
select LAPIC_MONOTONIC_TIMER
select CPU_INTEL_COMMON
# Microcode header files are delivered in FSP package
select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
choice
prompt "Rangeley CPU Stepping"
default FSP_MODEL_406DX_B0
config FSP_MODEL_406DX_A1
bool "A1"
config FSP_MODEL_406DX_B0
bool "B0"
endchoice
config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/fsp_model_406dx/bootblock.c"
#set up microcode for rangeley POSTGOLD4 release
config CPU_MICROCODE_HEADER_FILES
string
default "../intel/cpu/rangeley/microcode/microcode-m01406d000e.h ../intel/cpu/rangeley/microcode/microcode-m01406d8128.h"
endif #CPU_INTEL_FSP_MODEL_406DX
|
