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##
## This file is part of the coreboot project.
##
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config CPU_INTEL_FSP_MODEL_406DX
bool
if CPU_INTEL_FSP_MODEL_406DX
config CPU_SPECIFIC_OPTIONS
def_bool y
select PLATFORM_USES_FSP1_0
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SSE2
select UDELAY_LAPIC
select SUPPORT_CPU_UCODE_IN_CBFS
select PARALLEL_CPU_INIT
select TSC_SYNC_MFENCE
select LAPIC_MONOTONIC_TIMER
choice
prompt "Rangeley CPU Stepping"
default FSP_MODEL_406DX_B0
config FSP_MODEL_406DX_A1
bool "A1"
config FSP_MODEL_406DX_B0
bool "B0"
endchoice
config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/fsp_model_406dx/bootblock.c"
config ENABLE_VMX
bool "Enable VMX for virtualization"
default n
config HAVE_CPU_MICROCODE_FILE
bool "Add microcode file"
help
The microcode binary
config CPU_MICROCODE_FILE
string "Path and filename of CPU microcode"
default "microcode.bin"
depends on HAVE_CPU_MICROCODE_FILE
help
The path and filename of the file containing the CPU microcode.
endif #CPU_INTEL_FSP_MODEL_406DX
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