index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
User &
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
cpu
/
intel
/
car
/
core2
Mode
Name
Size
-rw-r--r--
cache_as_ram.S
4179
log
plain
