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config CPU_AMD_MODEL_10XXX
bool
select ARCH_X86
select SSE
select SSE2
select MMCONF_SUPPORT_DEFAULT
select TSC_SYNC_LFENCE
select UDELAY_LAPIC
if CPU_AMD_MODEL_10XXX
config NUM_IPI_STARTS
int
default 1
config CPU_ADDR_BITS
int
default 48
config DCACHE_RAM_BASE
hex
default 0xc4000
config DCACHE_RAM_SIZE
hex
default 0x0c000
config UDELAY_IO
bool
default n
config SET_FIDVID
bool
default y
config MAX_PHYSICAL_CPUS
int
default 1
config LIFT_BSP_APIC_ID
bool
default n
if SET_FIDVID
config SET_FIDVID_DEBUG
bool
default y
config SET_FIDVID_STORE_AP_APICID_AT_FIRST
bool
default y
config SET_FIDVID_CORE0_ONLY
bool
default n
# 0: all cores
# 1: core 0 only
# 2: all but core 0
config SET_FIDVID_CORE_RANGE
int
default 0
endif # SET_FIDVID
config UDELAY_LAPIC_FIXED_FSB
int
default 200
config UPDATE_CPU_MICROCODE
bool
default y
config UPDATE_CPU_MICROCODE
bool "Update CPU microcode"
default y
depends on EXPERT && CPU_AMD_MODEL_10XXX
help
Select this to apply patches to the CPU microcode provided by
AMD without source, and distributed with coreboot, to address
issues in the CPU post production.
Microcode updates distributed with coreboot are not necessarily
the latest version available from AMD. Updates are only applied
if they are newer than the microcode already in your CPU.
Unselect this to let Fam10h CPUs run with microcode as shipped
from factory. No binary microcode patches will be included in the
coreboot image in that case, which can help with creating an image
for which complete source code is available, which in turn might
simplify license compliance.
Microcode updates intend to solve issues that have been discovered
after CPU production. The common case is that systems work as
intended with updated microcode, but we have also seen cases where
issues were solved by not applying the microcode updates.
Note that some operating system include these same microcode
patches, so you may need to also disable microcode updates in
your operating system in order for this option to matter.
endif # CPU_AMD_MODEL_10XXX
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