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#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
config CPU_AMD_AGESA
bool
default y if CPU_AMD_AGESA_FAMILY10
default y if CPU_AMD_AGESA_FAMILY12
default y if CPU_AMD_AGESA_FAMILY14
default y if CPU_AMD_AGESA_FAMILY15
default y if CPU_AMD_AGESA_FAMILY15_TN
default n
select TSC_SYNC_LFENCE
if CPU_AMD_AGESA
config XIP_ROM_SIZE
hex
default 0x100000
help
Overwride the default write through caching size as 1M Bytes.
On some AMD paltform, one socket support 2 or more kinds of
processor family, compiling several cpu families agesa code
will increase the romstage size.
In order to execute romstage in place on the flash rom,
more space is required to be set as write through caching.
source src/cpu/amd/agesa/family10/Kconfig
source src/cpu/amd/agesa/family12/Kconfig
source src/cpu/amd/agesa/family14/Kconfig
source src/cpu/amd/agesa/family15/Kconfig
source src/cpu/amd/agesa/family15tn/Kconfig
endif # CPU_AMD_AGESA
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