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config CPU_ALLWINNER_A10
bool
default n
if CPU_ALLWINNER_A10
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_BOOTBLOCK_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
select BOOTBLOCK_CONSOLE
select CPU_HAS_BOOTBLOCK_INIT
# The "eGON.BT0" header takes 32 bytes
config BOOTBLOCK_BASE
hex
default 0x20
config BOOTBLOCK_ROM_OFFSET
hex
default 0x00
config CBFS_HEADER_ROM_OFFSET
hex
default 0x10
# This is the maximum size bootblock that the BROM will load. If the bootblock
# gets larger, this will generate a build failure, rather than a silent
# "coreboot won't run" failure.
# Normally, we would place romstage at 0x5fe0, but we place it a little lower to
# satisfy the 64 byte alignment.
config CBFS_ROM_OFFSET
default 0x5fc0
# 16 MiB above ramstage, so there is no overlap
config ROMSTAGE_BASE
hex
default 0x41000000
# Keep the stack in SRAM block A2.
# SRAM blocks A1 (0-16KiB) and A2 (16KiB-32KiB) are always accessible to the
# CPU. This gives us 32KiB of SRAM to boot with. The BROM bootloader will use up
# to 24KiB to load our bootblock, which leaves us the area from 24KiB to 32KiB
# to use however we see fit.
config STACK_TOP
hex
default 0x00008000
config STACK_BOTTOM
hex
default 0x00006000
config STACK_SIZE
hex
default 0x00002000
## TODO Change this to some better address not overlapping bootblock when
## cbfstool supports creating header in arbitrary location.
config CBFS_HEADER_ROM_OFFSET
hex "offset of master CBFS header in ROM"
default 0x40
config SYS_SDRAM_BASE
hex
default 0x40000000
endif # if CPU_ALLWINNER_A10
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